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Interfaces and Virtual Interfaces
Chapter - Mar 15, 2018 VM Team
The SystemVerilog interface provides a convenient means of organizing related signals into a container in order to simplify connections between modules. An interface may be declared with or without ports. If it is declared with ports, then those ports need to be assigned to signals when the interface is instantiated.
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UVM
Cookbook - Mar 15, 2018 Verification Methodology Team
The (2018) version conforms to the IEEE 1800.2 UVM Standard and promotes an emulation-friendly UVM testbench architecture that promotes reuse of your UVM environment as your project moves from simulation to emulation and beyond. Find all the UVM methodology advice you need in this comprehensive and vast collection.
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UVM Cookbook
Resource (Cookbook) - Mar 15, 2018 Verification Methodology Team
The UVM Cookbook conforms to the IEEE 1800.2 UVM Standard and promotes an emulation-friendly UVM testbench architecture that promotes reuse of your UVM environment as your project moves from simulation to emulation and beyond.
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UVM Sequences
Chapter - Mar 15, 2018 VM Team
In testbenches written in traditional HDLs like Verilog and VHDL, stimulus is generated by layers of sub-routine calls which either execute time consuming methods (i.e. Verilog tasks or VHDL processes or procedures) or call non-time consuming methods (i.e. functions) to manipulate or generate data.
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UVM Configuration Database
Chapter - Mar 15, 2018 VM Team
The uvm_config_db is a UVM utility class that is used to pass configuration data objects between component objects in a UVM testbench. Any call to the uvm_config_db is parameterized with the type of the data object that is stored or retrieved. To store an object in the uvm_config_db, its set() method is used, and to retrieve an object from the uvm_config_db, its get() method is used.
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Handling Parameterization
Chapter - Mar 15, 2018 VM Team
Parameters are commonly used to configure design IP and interfaces. From the perspective of VIP, parameters usually affect the width of bus fields or the number of channels or lanes in use. SystemVerilog interfaces may be parameterized and, when they are, their virtual interface handles also need to be parameterized.
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Virtual Interface BFMs
Chapter - Mar 15, 2018 VM Team
In order to make verification components reusable between testbenches they are organized as uvm_agents with an associated signal interface. These are also referred to as UVCs (Universal Verification Components). Inside the uvm_agent, there are two types of uvm_components that interact with the virtual interface.
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Abstract-Concrete Class Connections
Chapter - Mar 15, 2018 VM Team
An alternative to using a virtual interface handle for DUT to UVM testbench connections is to use an abstract-concrete class pair. The abstract version of the class defines templates for all the methods that are available in the BFM. The concrete version of the class is declared in the BFM and it extends the abstract version, providing an implementation of the methods. The handle of the concrete class is assigned to the abstract handle in the agent classes via the uvm_config_db.
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Connecting the Testbench to the DUT
Chapter - Mar 15, 2018 VM Team
The UVM testbench objects cannot make a direct connection to the DUT signals in order to drive or sample them. The connection between an agent’s driver and monitor component objects and the DUT is indirected through one or more BFM components that have static signal ports. In this section of the UVM cookbook we consider the problem of connecting the UVM testbench to the RTL DUT.
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Messaging in Sequences
Chapter - Mar 12, 2018 Verification Methodology Team
Sequences typically use messaging, either for debug, traceability or to report on the outcome of a built-in checking mechanism.
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Messaging
Chapter - Mar 12, 2018 Verification Methodology Team
The UVM messaging system provides an infrastructure for printing messages in a consistent format from a UVM testbench
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UVM Report Catcher
Chapter - Mar 12, 2018 Verification Methodology Team
There are situations where you may need to change a message generated by the messaging system, and the uvm_report_catcher is built-in call-back mechanism for doing this.
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Command-Line Verbosity Control
Chapter - Mar 12, 2018 Verification Methodology Team
There are several UVM plusargs that can be used to control messaging verbosity, actions and severity from the command line.
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Testing Message Status
Chapter - Mar 12, 2018 Verification Methodology Team
At the end of a UVM simulation, the report server issues a messaging summary to the transcript of the simulation.
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Using Messaging
Chapter - Mar 12, 2018 Verification Methodology Team
The recommended way to use the UVM messaging system is to use the message macros, since they automatically insert the file name and line number of the message source into the UVM message string which is useful for debugging
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Complex Address Maps
Chapter - Mar 09, 2018 Verification Methodology Team
In SoC design, the address mapping of registers and memory is often more complex than a single map.
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Accellera UVM 1.2 Summary
Chapter - Mar 09, 2018 Verification Methodology Team
Cookbook topics which link to this page are affected by backwards compatibility issues or migration issues, when the Accellera UVM 1.2 release is used. Check the categories below for sources of information and advice, and a summary of the changes involved in migrating from UVM 1.1x to UVM 1.2.
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Comprehensive Metrics-Based Methodology to Achieve Low Power SoCs
Webinar - Mar 07, 2018 Ellie Burns
In this session, you will be introduced to the tutorial agenda and markets, metrics, dimensions and Lifecyle of low-power design and verification.
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Questa Verification IP Integration
Session - Mar 04, 2018 Dave Aerne
In this session, you will learn how to integrate Questa Verification IP (QVIP) within your UVMF testbench.
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Questa Verification IP Integration
Resource (Slides (.PDF)) - Mar 04, 2018 Dave Aerne
In this session, you will learn how to integrate Questa Verification IP within your UVMF testbench.
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UVMF and Emulation
Session - Mar 04, 2018 Mike Horn
The UVMF works out of the box with both simulators and emulators, but how? This session helps you to understand Testbench Acceleration and how the UVMF gets you there.
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Configuring Memory Read Completions Sent by PCIe® QVIP
Article - Mar 01, 2018 Arushi Jain, Rajat Rastogi - Siemens EDA
In real hardware systems, the read completion sizes for upstream read requests (initiated towards the root complex) are characteristics of the processor in use and the maximum payload size (request payload size) limitations of endpoint as a receiver. Out of various aspects to be considered while creating a read completion, important aspects of data associated with it are byte enables (valid data to be read), value of the read request, and address at which the request is initiated.
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SATA Specification 3.3 Gaps Filled by SATA QVIP
Article - Mar 01, 2018 Naman Saxena, Nitish Goel, Rajat Rastogi - Siemens EDA
Developed to supersede Parallel ATA (PATA), the Serial ATA (SATA) protocol provides higher signaling rates, reduced cable sizes, and optimized data transfers for the connections between host bus adaptors and mass storage devices. SATA is a high-speed serial protocol with a point-to-point connection between the host and each of its connected devices. It is a layered protocol comprising of a command and application layer, transport layer, link layer, and physical layer.
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Power Aware Static Verification: From Power Intent to Microarchitectural Checks of Low Power Designs - Part 1
Article - Mar 01, 2018 Progyna Khondkar
Power Aware Static Verification is primarily targeted to uncover the power aware structural issues that affects designs physically in architectural and microarchitectural aspects. The structural changes that occur in a PA design are mostly due to physical insertions of special power management and MV cells; such as power switches (PSW), isolation (ISO), level shifter (LS), enable level shifter (ELS), repeaters (RPT), and retentions flops (RFF).
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A Hierarchical and Configurable Strategy to Verify RISC-V based SoCs
Article - Mar 01, 2018 Dr. Mike Bartley
This article outlines a hierarchical and configurable verification strategy for RISC-V based IP and SoCs. A three-level (unit, core and SoC) hierarchy is proposed for testbenches. Each level of the hierarchical testbench is configurable for both architectural and micro-architectural parameters. At the heart of the verification strategy is an ISG (Instruction Stream Generator) and a UVM testbench.