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DAC 2016 Academy PDF Presentation: Get a Head Start on the New UVM Standard
Resource - Jun 20, 2016 by
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Marking Milestones: In Life and in Technology
Article - Jun 14, 2016 by Verification Horizons
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SW-HW Pipe
Resource (Pattern) - Jun 10, 2016 by Harry Foster
The SW-HW Pipe Pattern is an implementation pattern that provides a buffered one-way communication channel between separated HVL and HDL module hierarchies in a dual-domain partitioned testbench. Writing to and reading from the pipe can be done at any rate. Writes block if the pipe is full. Data written to an empty pipe is available for reading on the next clock cycle. Reading from an empty pipe has a well-defined behavior.
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How Formal Techniques Can Keep Hackers from Driving You into a Ditch
Article - Jun 01, 2016 by Joe Hupcey
In this article we will show how a mathematical, formal analysis technique can be applied to ensure that this secure storage cannot (A) be read by an unauthorized party or accidentally “leak” to the outputs or (B) be altered, overwritten, or erased by unauthorized entities. We will include a real-world case study from a consumer electronics maker that has successfully used this technology to secure their products from attacks 24/7/365.
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Simplifying HDCP Verification Using Questa Verification IP
Article - Jun 01, 2016 by Raman Jain, Priya Minocha - Siemens EDA
This article describes various challenges in the field of verifying and debugging HDCP protected interfaces (HDMI and DisplayPort), and how Mentor’s QVIP makes this task easier for users by providing simple to use APIs and debug messages.
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No RTL Yet? No Problem. UVM Testing a SystemVerilog Fabric Model
Article - Jun 01, 2016 by Rich Edelman
SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/VALID channels.
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Accelerating Networking Products to Market
Article - Jun 01, 2016 by Dr. Lauro Rizzatti - Rizzatti LLC
Take a step down the stack beyond optical networks, switches, routers and software-defined networking to consider the networking system on chip (SoC), the brains of the network infrastructure.
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Physical Verification of FPGAs in Accordance with an Aerospace DO-254 Methodology Flow
Article - Jun 01, 2016 by Francis Raguin - Barco N.V.
RTCA DO-254 - Guidance document for the development of hardware components for airborne equipment – requires the functional behavior of FPGAs to be silicon proven on the final application hardware:
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Extending UVM Verification Models for the Analysis of Fault Injection Simulations
Article - Jun 01, 2016 by Dan Alexandrescu, Adrian Evans - IROC Technologies
In this article, we show how the components of a UVM functional verification environment can easily be extended to record additional information about the types of errors that have occurred. This additional information can be used to classify failing tests based on their system level impact (e.g. Silent Data Corruption, Detected Uncorrected Error, etc.). We present an architecture that can be implemented on the Questa Verification Platform for designs with UVM DVE.
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Solve UVM Debug Problems with the UVM Vault
Article - Jun 01, 2016 by Srinivasan Venkataramanan, Ajeetha Kumari - VerifWorks
Universal Verification Methodology (UVM) is the industry standard verification methodology for Verification using SystemVerilog (SV). UVM provides means of doing verification in a well-defined and structured way. It is a culmination of well-known ideas, thoughts and best practices.
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Parameterized UVM Tests
Resource (Pattern) - May 02, 2016 by Harry Foster
Parameters used in a design in most cases must also be used in a testbench to ensure proper connections and communication can be performed. Parameterized UVM tests (which are not available by default) provide an easy mechanism for sharing of parameters.
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Classes
Session - Apr 27, 2016 by Dave Rich
This session provides a short history of OOP and explains some of the terminology used by SystemVerilog that enables it.
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Classes
Resource (Slides (.PDF)) - Apr 27, 2016 by Dave Rich
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Inheritance and Polymorphism
Session - Apr 27, 2016 by Dave Rich
This session explains the key features and benefits of inheritance, polymorphism, and virtual methods along with examples of their use.
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Inheritance and Polymorphism
Resource (Slides (.PDF)) - Apr 27, 2016 by Dave Rich
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OOP Design Pattern Examples
Resource (Slides (.PDF)) - Apr 27, 2016 by Dave Rich
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OOP Design Pattern Examples
Session - Apr 27, 2016 by Dave Rich
This session provides examples of design patterns along with parameterized classes extensively used by people writing re-usable verification environments with the UVM.
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Advanced Validation and Functional Verification Techniques for Complex Low Power SoCs
Resource (Slides (.PDF)) - Apr 13, 2016 by Joe Hupcey
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Questa Visualizer - Power Aware Debug
Demo - Mar 18, 2016 by Chuck Seeley
In this demo, you will learn the UPF based Power Aware Debug features available in Visualizer with Questa PASim.
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Introducing the Verification Academy Patterns Library!
Resource (Verification Horizons Blog) - Mar 16, 2016 by Harry Foster
If you have been involved in either software or advanced verification for any length of time, then you probably have heard the term Design Patterns . In fact, the literature for many of today’s testbench verification methodologies (such as UVM) often reference various software or object-oriented related patterns in their discussions.
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Walking
Resource (Pattern) - Mar 16, 2016 by Harry Foster
The walking pattern will be applicable for anyone focused on integration verification to effectively verify connectivity between various modules such as Address and Data bus. These are very commonly patterns used in stimulus and verification of RAM address and bus connectivity.
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Strategy
Resource (Pattern) - Mar 16, 2016 by Harry Foster
This pattern helps implement one of the basic principles of Object Oriented programming and defines a family of algorithms, encapsulate each one, and make them interchangeable. Strategy lets the algorithm vary independently from clients that use it.
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No RTL Yet? No Problem - UVM Testing a SystemVerilog Fabric Model
Resource (Paper (.PDF)) - Mar 15, 2016 by Rich Edelman
SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/VALID channels.
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Certus™ Silicon Debug: Don’t Prototype Without It
Article - Mar 07, 2016 by Verification Horizons
FPGA PROTOTYPE RUNNING—NOW WHAT? Well done team; we've managed to get 100's of millions of gates of FPGA-hostile RTL running at 10MHz split across a dozen FPGAs. Now what? The first SoC silicon arrives in a few months so let's get going with integrating our software with the hardware, and testing the heck out of it. For that, we'll need to really understand what's going on inside all those FPGAs. Ah, there's the rub.
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Reusable Verification Framework
Article - Mar 03, 2016 by Verification Horizons
Testbenches written in SystemVerilog and UVM face the problem of configurability and reusability between block- and system-level. Whereas reuse of UVCs from a block- to a system-level verification environment is relatively easy, the same cannot be said for the UVC's connection to the harness: The interfaces that these UVCs need changes from connections to primary inputs and outputs at block level to a set of hierarchical probes into the DUT at system level. This requires a re-write of all interface connections and hinders reuse.