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2072 Results
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Portable Stimulus from IP to SoC - Achieve More Verification
Resource (Slides (.PDF)) - Jul 26, 2018 by Matthew Ballance
This session will explain the buzz about the emerging Accellera Portable Stimulus Standard and how users have long been applying Portable Stimulus techniques across block, subsystem, and SoC-level environments to improve their verification productivity.
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No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!
Resource (Recording) - Jul 26, 2018 by Kurt Takara
In this session we will share a real world case study of how the customer applied Questa CDC at the RTL level, then Questa Signoff CDC for gate-level CDC and glitch detection to wring out 3 glitches among millions of signals. (One of the glitch sources found was one that they had suspected; but the other two were a complete surprise.)
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Comprehensive CDC Verification with Advanced Hierarchical Data Models
Article - Jun 29, 2018 by Ping Yeung
The size and complexity of designs, and the way they are assembled, is changing the clock-domain crossing (CDC) verification landscape. It is now common for these complex SoCs to have hundreds of asynchronous clocks.
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Creating SoC Integration Tests with Portable Stimulus and UVM Register Models
Article - Jun 29, 2018 by Matthew Ballance
Writing and reading registers is the primary way that the behavior of most IPs is controlled and queried. As a consequence of how fundamental registers are to the correct operation of designs, register tests are a seemingly-simple but important aspect of design verification and bring-up. At IP level, the correct implementation of registers must be verified – that they are accessible from the interfaces on the IP block and that they have the correct reset levels.
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It’s Not My Fault! How to Run a Better Fault Campaign Using Formal
Article - Jun 29, 2018 by Doug Smith
The ISO 26262 automotive safety standard requires evaluation of safety goal violations due to random hardware faults to determine diagnostic coverages (DC) for calculating safety metrics. Injecting faults using simulation may be time-consuming, tedious, and may not activate the design in a way to propagate the faults for testing.
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Coverage Driven Verification of NVMe Using Questa VIP (QVIP)
Article - Jun 29, 2018 by Anurag Singh - Siemens EDA
Verification planning requires identification of the key features from the design specification along with prioritization and testing of the functionality that leads to the development of a coverage model.
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Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs
Article - Jun 29, 2018 by Progyna Khondkar
Part I of this article provided a consolidated approach to understand verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requirements, statically on the structures of the design.
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Three Main Components to Look for in Your Emulation Platform
Article - Jun 29, 2018 by Vijay Chobisa
A significant evolution is underway in SoC verification and validation. The complexity of SoC designs has resulted in the need to perform both comprehensive verification as well as system-level validation very early in the design cycle, often before stable RTL code is available for the entire design. This same complexity has also created the need for extensive internal visibility into the design to understand subtle problems that can occur during silicon bring-up.
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Complex Addressable Registers in Mission Critical Applications
Article - Jun 29, 2018 by Ishanee Bajpai - Agnisys
In this article, we will discuss some complex registers that we have seen our customers use in mission-critical applications.
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RTL Glitch Verification
Article - Jun 29, 2018 by Ajay Daga - FishTail Design Automation
It is important that certain timing endpoints on a design are safe from glitches. For example, it is necessary that an asynchronous reset never have a glitch that momentarily resets a flop. It is also necessary that multi-cycle paths are safe from glitches, i.e., it should not be the case that while a cycle accurate simulation of the RTL shows correct multi-cycle behavior, once delays are accounted for a glitch can propagate along the path resulting in a single-cycle path.
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UVM-based Verification of a RISC-V Processor Core Using a Golden Predictor Model and a Configuration Layer
Article - Jun 29, 2018 by Marcela Zachariášová, Luboš Moravec - Codasip Ltd.
In this article, Codasip and Siemens EDA aim to describe their methodology of effective verification of RISC-V processors, based on a combination of standard techniques, such as UVM and emulation, and new concepts that focus on the specifics of the RISC-V verification, such as configuration layer, golden predictor model, and FlexMem approach.
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Virtual Method Upcasting & Downcasting And Their Use In UVM
Resource (Slides (.PDF)) - Jun 25, 2018 by Cliff Cummings
This session shows how upcasting and downcasting work and how they are frequently used in UVM testbench environments.
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Virtual Method Upcasting & Downcasting And Their Use In UVM
Conference - Jun 25, 2018 by Cliff Cummings
"Upcasting is casting to a supertype, while downcasting is casting to a subtype. Upcasting is always allowed, but downcasting involves a type check … and can throw a ClassCastException" This session shows how upcasting and downcasting work and how they are frequently used in UVM testbench environments.
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What is Formal, and How It Works Under-the-Hood
Track - May 14, 2018 by Doug Smith
It’s common knowledge that formal property verification – “formal”, for short – delivers exhaustive results. In a nutshell, formal tools statically analyze a design’s behavior with respect to a given set of properties, exhaustively exploring all possible input sequences in a breadth-first search manner to uncover design errors that would otherwise be missed.
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Instant Formal Expert
Session - May 14, 2018 by Dr. Jeremy Levitt
What are formal property checking engines and how do they work? Why are they incredibly powerful for some properties, but not so good for others? What's the state of the art and what's coming in the near future? In this session, we'll review the fundamentals as well as the recent breakthroughs that are driving advances in performance and capacity. Join us to instantly become a formal expert!
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What is Formal, Anyway
Resource (Slides (.PDF)) - May 14, 2018 by
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Instant Formal Expert
Resource (Slides (.PDF)) - May 14, 2018 by
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What is Formal, Anyway?
Session - May 14, 2018 by Doug Smith
In this session, you will learn what formal property checking is about: how formal differs from simulation, how constraints on expected inputs apply in the formal world, how it provides exhaustive results, and more.
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Running Simulations
Resource (Slides (.PDF)) - Apr 16, 2018 by Jonathan Craft
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Running Simulations
Session - Apr 16, 2018 by Jonathan Craft
In this session, you will learn how to run individual UVMF simulations in both batch and debug mode.
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UVMF & Emulation
Session - Apr 16, 2018 by Mike Horn
The UVMF works out of the box with both simulators and emulators, but how? This session helps you to understand Testbench Acceleration and how the UVMF gets you there.
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UVMF & Emulation
Resource (Slides (.PDF)) - Apr 16, 2018 by Mike Horn
The UVMF works out of the box with both simulators and emulators, but how? This session helps you to understand Testbench Acceleration and how the UVMF gets you there.
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Basic Abstraction Techniques
Resource (Slides (.PDF)) - Apr 14, 2018 by
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Sequence Categories
Resource (Slides (.PDF)) - Apr 12, 2018 by Bob Oden
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Sequence Categories
Session - Apr 12, 2018 by Bob Oden
In this session, you will learn the roles and responsibilities of the sequence categories and that sequences within UVMF are divided into three categories: interface, environment, and testbench.