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Smoothing the Path to Software-Driven Verification with Portable Stimulus
Article - Jun 28, 2017 by Matthew Ballance
Designs are becoming more complex and increasingly include a processor – and often multiple processors. Because the processor is an integral part of the design, it's important to verify the interactions between software running on the processor and the rest of the design.
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On-Chip Debug – Reducing Overall ASIC Development Schedule Risk
Article - Nov 01, 2015 by Eric Rentschler - Siemens EDA
With ASIC complexity on the increase and unrelenting time-to-market pressure, many silicon design teams still face serious schedule risk from unplanned spins and long post-silicon debug cycles. However, there are opportunities on both the pre-silicon and post-silicon sides that can be systematically improved using on-chip debug solutions.
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Evolving the Use of Formal Model Checking in SoC Design Verification
Article - Mar 11, 2015 by Ram Narayan
Project RAPID is a hardware-software co-design initiative in Oracle Labs that uses a heterogeneous hardware architecture combined with architecture-conscious software to improve the energy efficiency of database-processing systems.
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Caching in on Analysis
Article - Oct 01, 2013 by Mark Peryer
The on-chip bus interconnect has become a critical subsystem of a System On a Chip (SoC). Its function is to route data between different parts of the system at a rate that allows the system to meet its performance goals.
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Is Intelligent Testbench Automation For You?
Article - Jun 15, 2012 by Mark Olen
Intelligent Testbench Automation (iTBA) is being successfully adopted by more verification teams every day. There have been multiple technical papers demonstrating successful verification applications and panel sessions comparing the merits to both Constrained Random Testing (CRT) and Directed Testing (DT) methods. Technical conferences including DAC, DVCon, and others have joined those interested in better understanding this new technology.
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An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench
Article - Mar 02, 2016 by Shaela Rahman - Baker Hughes
FPGA designs are becoming too large to verify by visually checking waveforms, as the functionality has become beyond easy comprehension.
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How Do You “Qualify” Tools for DO-254 Programs?
Article - Mar 02, 2022 by Jake Wiltgen
Tools used in the design and verification of electronics have played a massive role in the dramatic evolution of these devices over the past few decades. After all, there is a limit to the amount of work and detail that even a good aerospace engineer can handle, but add the use of tools, and the sky (pun intended) is the limit.
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AMS Verification for High Reliability and Safety Critical Applications
Article - Oct 01, 2013 by Martin Vlach
Today, very high expectations are placed on electronic systems in terms of functional safety and reliability. Users expect their planes, automobiles, and pacemakers to work perfectly, and keep on working for years. A reboot of a smartphone is annoying, but rebooting the airplane or car electronics while underway could be catastrophic, and a glitch in an implanted medical device could be life threatening.
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DO-254 Testing of High-Speed FPGA Interfaces
Article - Jun 06, 2015 by Nir Weintroub, Sani Jabsheh - Verisense
As the complexity of electronics for airborne applications continues to rise, an increasing number of applications need to comply with the RTCA DO-254 / EUROCAE ED-80 standard for certification of complex electronic hardware, which includes FPGAs and ASICs.
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The Need for Speed: Understanding Design Factors that Make Multi-core Parallel Simulations Efficient
Article - Jun 01, 2013 by Shobana Sudhakar
The intent of this article is to educate customers and guide them to understand what makes a design multicore friendly. This can help customers write designs and testbenches to be more suited for parallel simulations. Cases of success and failures of QuestaSim MC2 deployments and the lessons learned from them form the basis of our analysis and substantiate our suggestions in this article.
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How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety
Article - Dec 05, 2017 by Dan Alexandrescu, Adrian Evans, Maximilien Glorieux - IROC Technologies
In this article, we present a working example, implemented using the Questa Verification Platform where a 32-bit RISC V CPU has been subjected to an extensive static and dynamic failure analysis process, as a part of a standard-mandated functional safety assessment.
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VHDL-2008: Why It Matters
Article - Oct 01, 2012 by Jim Lewis
This article overviews the changes and the value they bring to your design process. Topics are categorized into three major sections: testbench, RTL, and packages/operators.
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Physical Verification of FPGAs in Accordance with an Aerospace DO-254 Methodology Flow
Article - Jun 01, 2016 by Francis Raguin - Barco N.V.
RTCA DO-254 - Guidance document for the development of hardware components for airborne equipment – requires the functional behavior of FPGAs to be silicon proven on the final application hardware:
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Stimulating Simulating: UVM Transactions
Webinar - Aug 26, 2020 by Chris Spear
In this session, you will learn how to create classes for UVM transactions, also known as sequence items. You will also be shown how to add new functionality to a transaction, by extending the class and much more.