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102 Results

Memory Softmodels - The Foundation of Validation Accuracy

Article - Oct 26, 2020 Ridham Kothari - Siemens EDA

As always, we must continue to reduce the time-to-market of SoCs and complex systems. An FPGA prototype implementation of these systems can be used as a basis for early software or firmware development, hardware-software co-verification and system validation, and all this can be achieved before actual silicon is available.
Best Practices for FPGA and ASIC Development

Article - Jun 16, 2014 Josh Rensch - Siemens EDA

This is an overview of best practices for FPGA or ASIC design, assuming a traditional waterfall development process. There are four development phases: PLAN, EXECUTE, VERIFY and SUPPORT. A review step is recommended between each phase, as prescribed by DO-254. These concepts can be used in alternative methodologies, like Agile.
"Hug the Debug" – Before It’s Too Late

Article - Sep 01, 2021 Sumit Vishwakarma

Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by the global chip shortage, especially in the automotive industry.
Cut Weeks From Debug: Rapid First – Level Bug Hunting with Inspect and Check X

Webinar - Jan 29, 2026 Bobana Brzacki

In this webinar we introduce intuitive 'push-button' bug-hunting tools, Inspect and Check X, designed to transform your verification process. Join us for a practical deep dive into their core functionalities, demonstrating their efficient workflow from initial setup to insightful results analysis. You will gain a clear understanding of how these powerful solutions empower them to rapidly identify and resolve first-level design bugs, ensuring a more robust design and accelerated time-to-market.
Enabling Model-Based Design for DO-254 Certification Compliance

Article - Mar 02, 2022 Jake Wiltgen

Engineers can use Model-Based Design for requirements analysis, algorithm design, automatic HDL code generation, and verification to produce airborne electronic hardware that adheres to the DO-254 standard. The proposed Model-Based Design approach for DO-254 combines tools from MathWorks® and Siemens EDA for both design and verification. This workflow supports development phases from concept through implementation, streamlining development, and reducing costs.
RISC-V Design Verification Strategy

Article - Oct 26, 2020 Dr. Mike Bartley

As the RISC-V architecture becomes increasingly popular, it is being adopted across a diverse range of products. From the development of in-house cores with specialized instructions, to functionally safe SoCs and security processors for a variety of verticals – RISC-V adoption brings several verification challenges that are discussed in this article, along with potential approaches and solutions.
The Democratization of Digital Methodologies for AMS Verification

Article - Jul 05, 2022 Sumit Vishwakarma

A mixed-signal design is a combination of tightly interlaced analog and digital circuitry. Next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern systems on chips (SoCs). There are two critical reasons for this trend.
What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You

Article - Sep 01, 2021 Tom Fitzpatrick

Preface: in May 2021 Siemens EDA acquired OneSpin Solutions, combining Siemens' Questa Formal products and expertise (with roots and team members from 0-In) with OneSpin’s “apps first” approach to key growth markets including Trust&Security, Safety, RISC-V, and FPGAs. The combination adds to a cohesive Siemens EDA verification solution spanning simulation, formal, emulation, and prototyping.
Verification Cookbook Glossary

Chapter - Mar 31, 2014 Verification Methodology Team

This page is an index to the glossary of various terms defined and used in the Cookbook.
Robustness Verification of ARINC708’s Manchester Codes in a DO-254 Project

Article - Jun 21, 2023 Emin Akgün, Hilal Güneren - ANKASYS

In this article, we will discuss the Display Data Bus of ARINC-708. The bus plays a critical role in terms of the pilot’s point of view. It requires a bi-phase Manchester encoding and decoding. For both Manchester coding and the bus protocol, some examples of possible error types are considered.
Hardware-Assisted Verification Through the Years

Article - Sep 01, 2021 Jean-Marie Brunet

A quick glance in today’s design verification toolbox reveals a variety of point tools supporting the latest system-on-chip (SoC) design development. When combined and reinforced by effective verification methodologies, these tools trace even the most hard-to-find bug, whether in software or in hardware. The focus on tools and delivering a tightly woven integration between complementary tools is a strategic focus at Siemens EDA.
Celebrating 10 Years of the UVM

Article - Mar 03, 2021 Mark Peryer

Version 1.0 of the UVM class library was released by Accellera at the end of February 2011, the result of a unique collaborative effort between fierce competitors (Siemens EDA, formerly Mentor Graphics, Cadence, and Synopsys) and a small number of activist user companies. The objective was to provide an industry standard SystemVerilog based verification methodology.
Smoothing the Path to Software-Driven Verification with Portable Stimulus

Article - Jun 28, 2017 Matthew Ballance

Designs are becoming more complex and increasingly include a processor – and often multiple processors. Because the processor is an integral part of the design, it's important to verify the interactions between software running on the processor and the rest of the design.
On-Chip Debug – Reducing Overall ASIC Development Schedule Risk

Article - Nov 01, 2015 Eric Rentschler - Siemens EDA

With ASIC complexity on the increase and unrelenting time-to-market pressure, many silicon design teams still face serious schedule risk from unplanned spins and long post-silicon debug cycles. However, there are opportunities on both the pre-silicon and post-silicon sides that can be systematically improved using on-chip debug solutions.
Evolving the Use of Formal Model Checking in SoC Design Verification

Article - Mar 11, 2015 Ram Narayan

Project RAPID is a hardware-software co-design initiative in Oracle Labs that uses a heterogeneous hardware architecture combined with architecture-conscious software to improve the energy efficiency of database-processing systems.
Caching in on Analysis

Article - Oct 01, 2013 Mark Peryer

The on-chip bus interconnect has become a critical subsystem of a System On a Chip (SoC). Its function is to route data between different parts of the system at a rate that allows the system to meet its performance goals.
Is Intelligent Testbench Automation For You?

Article - Jun 15, 2012 Mark Olen

Intelligent Testbench Automation (iTBA) is being successfully adopted by more verification teams every day. There have been multiple technical papers demonstrating successful verification applications and panel sessions comparing the merits to both Constrained Random Testing (CRT) and Directed Testing (DT) methods. Technical conferences including DAC, DVCon, and others have joined those interested in better understanding this new technology.
Questa Equivalent FPGA Retargeting Flow

Paper - Sep 10, 2023 Martin Rowe

This paper provides a methodology to apply equivalence checking solutions for design retargeting. This extends design life by migrating from obsolete FPGAs to newer technologies. This document contains a step-by-step description of multiple retargeting methods for various use cases. It is assumed the reader is familiar with the basics of the equivalence checking process using Questa™ Equivalent FPGA from Siemens EDA.
An Evaluation of the Advantages of Moving from a VHDL to a UVM Testbench

Article - Mar 02, 2016 Shaela Rahman - Baker Hughes

FPGA designs are becoming too large to verify by visually checking waveforms, as the functionality has become beyond easy comprehension.
How Do You “Qualify” Tools for DO-254 Programs?

Article - Mar 02, 2022 Jake Wiltgen

Tools used in the design and verification of electronics have played a massive role in the dramatic evolution of these devices over the past few decades. After all, there is a limit to the amount of work and detail that even a good aerospace engineer can handle, but add the use of tools, and the sky (pun intended) is the limit.
AMS Verification for High Reliability and Safety Critical Applications

Article - Oct 01, 2013 Martin Vlach

Today, very high expectations are placed on electronic systems in terms of functional safety and reliability. Users expect their planes, automobiles, and pacemakers to work perfectly, and keep on working for years. A reboot of a smartphone is annoying, but rebooting the airplane or car electronics while underway could be catastrophic, and a glitch in an implanted medical device could be life threatening.
DO-254 Testing of High-Speed FPGA Interfaces

Article - Jun 06, 2015 Nir Weintroub, Sani Jabsheh - Verisense

As the complexity of electronics for airborne applications continues to rise, an increasing number of applications need to comply with the RTCA DO-254 / EUROCAE ED-80 standard for certification of complex electronic hardware, which includes FPGAs and ASICs.
The Need for Speed: Understanding Design Factors that Make Multi-core Parallel Simulations Efficient

Article - Jun 01, 2013 Shobana Sudhakar

The intent of this article is to educate customers and guide them to understand what makes a design multicore friendly. This can help customers write designs and testbenches to be more suited for parallel simulations. Cases of success and failures of QuestaSim MC2 deployments and the lessons learned from them form the basis of our analysis and substantiate our suggestions in this article.
How Static and Dynamic Failure Analysis Can Improve Productivity in the Assessment of Functional Safety

Article - Dec 05, 2017 Dan Alexandrescu, Adrian Evans, Maximilien Glorieux - IROC Technologies

In this article, we present a working example, implemented using the Questa Verification Platform where a 32-bit RISC V CPU has been subjected to an extensive static and dynamic failure analysis process, as a part of a standard-mandated functional safety assessment.
VHDL-2008: Why It Matters

Article - Oct 01, 2012 Jim Lewis

This article overviews the changes and the value they bring to your design process. Topics are categorized into three major sections: testbench, RTL, and packages/operators.