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2072 Results
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CDC Verification: Beyond Structural Analysis
Webinar - Jul 29, 2021 by Mark Handover
In this session, we will cover the overall CDC methodology and cover CDC protocols and reconvergence in more details and show what could happen if these steps are skipped.
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Mitigating the Effects of Random Hardware Faults
Webinar - Jul 29, 2021 by Dirk Hansen
Random faults cannot be prevented so the goal there is to sufficiently tolerate them. With random faults you are really just trying to make sure that the product will fail safely when inevitably one of these random hardware faults occurs. In this session we will outline approaches on how to tackle systematic as well as random faults.
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AMS Functional Verification for Safety-Critical Automotive Applications
Webinar - Jul 29, 2021 by Sumit Vishwakarma
In this session, you will learn how Siemens EDA Symphony platform addresses today's nanometer mixed signal verification challenges for safety-critical automotive applications.
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A Path to Develop Safe ICs - Part 2
Webinar - Jul 29, 2021 by Stephanie Dournelle, Paul Williams - Siemens EDA
In this session you will learn that Siemens EDA has developed a platform that allows early collaboration between OEMs and their suppliers. It provides a clear definition of requirements and allows hardware and software functionality to be tested in a virtual environment long before silicon is available.
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A Path to Develop Safe ICs - Part 1
Webinar - Jul 29, 2021 by Stephanie Dournelle - Siemens EDA
In this session, you will learn that Siemens EDA helps customers adapt to the required development flows, develop safety collateral for their designs, and mitigate the risk of product failure in safety critical applications.
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Extending the Role of Test and In-System Test to Meet Automotive Safety and Security Requirements
Webinar - Jul 29, 2021 by Lee Harrison
In this session, we will show how Design For Test is expanding from its traditional role into one that includes the management of the entire silicon lifecycle, to become Silicon Lifecycle Solutions. Ensuring that ICs work safely as expected and are secure throughout their operational life.
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Hardware-Accelerated & Software-Driven Verification
Webinar - Jul 29, 2021 by Ajay Sharma
In this session we will talk about ease of adopting Emulation and various ways of using the powerful Apps that bring in software to improve accuracy of verification process.
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Automotive SOTIF Compliance for Arm with PAVE360
Webinar - Jul 29, 2021 by Antonio Priore - Arm, Joe Dailey - Siemens, Tapan Vikas - Siemens EDA
In this session, we will explain Safety Of The Intended Function (SOTIF) and demonstrate techniques to prove systems.
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Are Random Hardware Faults Common?
Webinar - Jul 29, 2021 by Dirk Hansen
In this session, you will be given an introduction of solutions to analysis failure modes resulting from random hardware faults. These can guide the user to unsafe areas of the design where safety mechanisms need to be inserted.
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Traceability for Automotive Standards Compliance
Webinar - Jul 29, 2021 by Darron May
In this session, you will learn how the combination of Siemens Polarion ALM Requirements Management and Questa Verification Management solve the lifecycle management and traceability requirements for Automotive projects.
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The Future of Automotive and its Impact on Safety
Session - Jul 29, 2021 by Ann Keffer
This session will provide a perspective on the impact to companies developing automotive ICs and serves as the introduction to the multi-part automotive safety webinar series covering many aspects of an automotive safety lifecycle.
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It’s Not My Fault! How to Run a Better Fault Campaign Using Formal
Resource (Paper (.PDF)) - Jul 21, 2021 by Doug Smith
The ISO 26262 automotive safety standard requires evaluation of safety goal violations due to random hardware faults to determine diagnostic coverages (DC) for calculating safety metrics. Injecting faults using simulation may be time-consuming, tedious, and may not activate the design in a way to propagate the faults for testing.
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Part II: Verification of PCIe® IP
Webinar - Jul 15, 2021 by Stephane Hauradou
In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.
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UVM Framework Release 2021.3
Resource (Tarball) - Jul 13, 2021 by Bob Oden
General Updates: General bug fixes and documentation updates Generator Updates: Added C data types for Mathworks® integration flow
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Sequential Logic Equivalence Checking
Track - Jul 06, 2021 by Jin Hou
In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.
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SLEC Introduction
Session - Jul 06, 2021 by Jin Hou
In this session, you will learn the concept of sequential logic equivalence checking (SLEC) and the common applications of SLEC.
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SLEC for Design Optimization
Session - Jul 06, 2021 by Jin Hou
In this session, you will learn how to use SLEC to verify functional equivalence between two RTL designs before and after optimization.
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SLEC for Bug Fix / ECO
Session - Jul 06, 2021 by Jin Hou
In this session, you will learn how to use SLEC to verify that bug fix/ ECO doesn’t introduce new bugs.
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SLEC for Low Power Clock Gating
Session - Jul 06, 2021 by Jin Hou
In this session, you will how to use SLEC to verify that the design works the same with and without added low power clock gating logic.
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SLEC for Safety Mechanism
Session - Jul 06, 2021 by Jin Hou
In this session, you will learn how to use SLEC to verify that the design’s safety mechanism handles faults as required.
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Formal Verification for DO-254 (and other Safety-Critical) Designs
Resource (Paper (.PDF)) - Jul 01, 2021 by Mark Eslinger
This document focuses on the issue of advanced verification and tool assessment for DO-254, specifically for the Siemens EDA Questa Formal Verification tool.
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Formal Verification for DO-254 (and other Safety-Critical) Designs
Paper - Jul 01, 2021 by David Landoll
DO-254 defines a process that hardware vendors must follow to get their hardware certified for use in avionics. All in-flight hardware (i.e., PLD, FPGA or ASIC designs) must comply with DO-254. This document focuses on the issue of advanced verification and tool assessment for DO-254, specifically for the Siemens EDA Questa Formal Verification tool.
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Understanding Formal Methods for Use in DO-254 Programs
Paper - Jul 01, 2021 by Harry Foster
This paper seeks to take the mystery out of the use of formal methods for hardware verification. We will first explain formal methods as clearly and concisely as possible. We will then look at the state of the industry and the changes over the last decade or so that have enabled the widespread use of formal methods for hardware verification. Finally, we will bring this information together and provide recommendations for using formal methods on a DO- 254 project.
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Understanding Formal Methods for Use in DO-254 Programs
Resource (Paper (.PDF)) - Jul 01, 2021 by Harry Foster
This paper seeks to take the mystery out of the use of formal methods for hardware verification. In this discussion, we will first explain formal methods as clearly and concisely as possible.
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Leveraging Advancements in UPF 3.1 for Effective Design and Verification
Webinar - Jun 23, 2021 by Gabriel Chidolue
In this session, you will learn about some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.