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ISO 26262 (69)
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VHDL (42)
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RISC-V (37)
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PSS (36)
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DAC (35)
IEEE 1801 (35)
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Questa One (34)
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WRG (33)
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Objects (32)
Power Domain (32)
Scoreboard (32)
DO-254 (31)
Verification Efficiency (31)
Bug Hunting (30)
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Metastability (30)
Modeling (30)
Reset-Domain Crossing (30)
TLM (30)
osmosis 2022 (30)
Accellera (29)
CDC Methodology (29)
Properties (29)
Register Model (29)
Reset Issues (29)
Safety Analysis (29)
ASIC (28)
Safety Architecture (28)
UVM Debug (28)
Analytics (27)
Classes (27)
Introduction to UVM (27)
Lint (27)
PCIe (27)
Patterns (27)
Requirements Traceability (27)
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Test Planning (27)
Design Optimization (26)
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Property Checks (26)
Verilog (26)
Waveform (26)
Archive (25)
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Asynchronous Clock (24)
Block Level (24)
Cookbook (24)
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Driver (24)
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Lifecycle (24)
Object Oriented Programming (24)
Testplan (24)
UVM Basics (24)
Co-Emulation (23)
Requirements (23)
osmosis 2024 (23)
Assurance (22)
Data-driven Verification (22)
FSM (22)
Non-Trivial Bug Escapes (22)
Performance (22)
VRM (22)
Big Data (21)
Collaborative Analysis (21)
Config_db (21)
Constrained Random Verification (21)
Covergroup (21)
Memory (21)
Netlist (21)
PCI Express (21)
Packages (21)
U2U (21)
osmosis 2023 (21)
Acceleration (20)
Advanced UVM (20)
C (20)
Constrained Random Stimulus (20)
Continuous Integration (20)
DFT (20)
Design Constructs (20)
Functional Verification Study (20)
Hardware Fault (20)
System Level (20)
X-Tracing (20)
Abstraction (19)
Data Types (19)
Interactive Mode (19)
Power States (19)
Proofs (19)
Python (19)
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Scenario Generation (19)
Verification Closure (19)
Verification Practice (19)
Verification Run Manager (19)
Virtual Interface (19)
API (18)
Arrays (18)
Automation (18)
Code Generator (18)
Configuration Database (18)
Controllers (18)
Coverage Points (18)
Interoperability (18)
Polymorphism (18)
Sequence Item (18)
Sequencer (18)
Advanced Debug Techniques (17)
CDC Analysis (17)
Chiplets (17)
Design for Test (17)
Electronic Systems (17)
Fault Injection (17)
Livesim (17)
Object-Oriented Programming in SystemVerilog (17)
Sequence Driver (17)
State Space (17)
Testbench Automation (17)
U2U Europe (17)
Virtual Sequences (17)
BFMs (16)
Continuous Integration System (16)
Gate-Level (16)
HLS (16)
Reset-Domain Checking (16)
SLEC (16)
Signal (16)
Data Models (15)
Expressions (15)
Inconclusives (15)
Intelligent Automation (15)
Power Intent (15)
QVIP Configurator (15)
Sub-system (15)
UCIe (15)
Universal Chiplet Interconnect Express (15)
Variable (15)
osmosis Europe 2025 (15)
ABV (14)
Assertion-Based Verification (14)
Automotive Functional Safety Forum (14)
COCOTB (14)
Customization (14)
DFT Verification (14)
Failure Analysis (14)
Fault Simulation (14)
Glitches (14)
Jenkins (14)
Macros (14)
March 2016 - Volume 12 Issue 1 (14)
Monitors (14)
NVMe (14)
Productivity Gap (14)
Register Layer Adapter (14)
Stimulus Generation (14)
UVMC Kit (14)
AXI (13)
Declaration (13)
Design Complexity (13)
FPGA Prototyping (13)
Formal Application (13)
Gate-Level Simulation (13)
Hardware Acceleration (13)
IC Reliability (13)
Multi-Die (13)
Python for Verification Series (13)
RDC Analysis (13)
Verification IQ (13)
X-Propagation (13)
ASIL (12)
Adoption Trends (12)
Agent (12)
Co-Simulation (12)
Coverage Models (12)
DVCon Japan (12)
Data Mining (12)
Environment Pattern (12)
Functional Correctness (12)
Hierarchical Components (12)
Interconnect (12)
Interrupts (12)
Operators (12)
Parameterized Classes (12)
Randomization (12)
September 2021 - Volume 17 Issue 2 (12)
Traceability (12)
Unit Testing (12)
Aerospace and Defense Verification Tech Day (11)
Analog (11)
Checkers (11)
Class Objects (11)
Configuration Object (11)
Connections (11)
Creating and Using Constrained Random (11)
DAC 2019 (11)
DPI-C (11)
Generation (11)
Interview (11)
June 2015 - Volume 11 Issue 2 (11)
June 2017 - Volume 13 Issue 2 (11)
Memory Models (11)
Methods (11)
Mixed-Signal Verification (11)
OVM (11)
PYUVM (11)
Predictive Analysis (11)
Processor Design Verification (11)
RDC Design (11)
Reachability Checks (11)
Register Package (11)
Test Environment (11)
Tool Assessment (11)
VIQ (11)
Verification Process Overview (11)
AMBA (10)
Backdoor Accesses (10)
Class Handles (10)
Class Reference (10)
Command API (10)
Convergence (10)
Deadlock (10)
Fault Analysis (10)
Fault Grading (10)
High Speed (10)
Implementation Model (10)
Inheritance (10)
Isolation (10)
July 2022 - Volume 18 Issue 2 (10)
June 2013 - Volume 9 Issue 2 (10)
Matlab (10)
Metrics-Driven (10)
Model Checking (10)
Parallel Simulation (10)
Proof Coverage (10)
Property Debug (10)
RDC Methodology (10)
Report (10)
Reset Architecture (10)
Root of Trust (10)
Safety Metrics (10)
Timing (10)
Unified Power Format (10)
Verification Architecture (10)
Verification Component (10)
osmosis 2025 (10)
1800.2 (9)
3DIC (9)
Bitstream (9)
Breakpoint (9)
CDC Path (9)
CDC Protocol (9)
Creating and Using Functional Coverage (9)
Curriculum (9)
Data Management (9)
Data Types and Procedural Statements (9)
Encapsulation (9)
Formal Assertion-Based Verification (9)
Hardware Security (9)
Hierarchical Sequences (9)
High-Level Synthesis (9)
Iterations (9)
June 2012 - Volume 8 Issue 2 (9)
June 2014 - Volume 10 Issue 2 (9)
June 2018 - Volume 14 Issue 2 (9)
Learning Paths (9)
Metastable (9)
Multi-Core Architectures (9)
PSL (9)
Parameter (9)
RDC Violations (9)
Reconvergence (9)
Reference Model (9)
Retention (9)
SPI (9)
Schematic (9)
Sequence-Driver Use Models (9)
Siemens Xcelerator Academy (9)
Skill Building (9)
Training (9)
UCDB (9)
UVM Stimulus, Tests, and Regressions (9)
VHDL-2008 (9)
Validation (9)
Whats New in Functional Verification (9)
AI Algorithms (8)
Algorithms (8)
B/C/R Script (8)
Clock Gating (8)
Coverage Goals (8)
Cross Coverage (8)
DMA Engine (8)
Design and Verification IP Forum (8)
Directed Test (8)
Ethernet (8)
Factory Pattern (8)
February 2013 - Volume 9 Issue 1 (8)
HDL Domain (8)
HPC (8)
HTML Docs (8)
June 2016 - Volume 12 Issue 2 (8)
March 2021 - Volume 17 Issue 1 (8)
Messaging (8)
Mixed-Signal Design (8)
Monitor (8)
OSCI (8)
OVM2UVM (8)
Occurrence Property Pattern (8)
Overrides (8)
Phasing (8)
Pipelined (8)
Power Analysis (8)
Power Logic (8)
Power Optimization (8)
Procedural Statements (8)
Release (8)
Reporting (8)
Reset Tree (8)
SVA (8)
Safety (8)
Scalable Verification (8)
Simulation Coverage (8)
State Machine (8)
State Transitions (8)
Supply Set (8)
Testing Strategies (8)
UALink (8)
UCIe 2.0 (8)
UVM Verification (8)
Waivers (8)
osmosis 2023 A&D (8)
ADAS (7)
Bind (7)
Cache Coherency (7)
Clocking Verification Challenges (7)
Conditionals (7)
Connecting the Testbench to the Design (7)
Conversion (7)
Data Transfer (7)
Design Assurance (7)
Design IP (7)
Design Integrity (7)
Diagnostic Coverage (7)
Error Injection (7)
Error Traces (7)
Execution Semantics and Synchronization (7)
Fork-Join (7)
Guidelines (7)
IP Blocks (7)
IP Security (7)
ISA (7)
Israel Static & Formal Tech Day (7)
July 2020 - Volume 16 Issue 2 (7)
LLMs (7)
Layering (7)
March 2015 - Volume 11 Issue 1 (7)
March 2022 - Volume 18 Issue 1 (7)
March 2023 - Volume 19 Issue 1 (7)
Migration (7)
Modules (7)
Non-Determinism (7)
November 2014 - Volume 10 Issue 3 (7)
November 2015 - Volume 11 Issue 3 (7)
Objections (7)
Order Property Pattern (7)
Parameterized Tests (7)
Pin Level (7)
Postsim (7)
Power Estimation (7)
Predictors (7)
Safety Verification (7)
Schematic Debug (7)
Sequential Analysis (7)
Siemens EDA (7)
Specification (7)
Static Checks (7)
Strategy (7)
Structural Analysis (7)
Sub-system Level (7)
Supply Network (7)
System Scaling (7)
TLM FIFOS (7)
Technology Scaling (7)
Test Generation (7)
Test Verification (7)
Testbench Architecture (7)
Testbench Customization in UVM (7)
Tool Qualification (7)
Transaction Recording (7)
VA Live 2023 - Huntsville (7)
Voltage Domain Crossing (7)
X-Checking (7)
X-Corruption (7)
XML (7)
AEH (6)
Address Mapping (6)
Appendix (6)
Artificial Neural Network (6)
Behavioral Modeling (6)
Computational Storage (6)
Coverage Intent (6)
Creating and Using a Test Plan (6)
DAC 2018 (6)
DDR (6)
December 2017 - Volume 13 Issue 3 (6)
December 2022 - Volume 18 Issue 3 (6)
Design Mitigation (6)
Design Patterns (6)
Digital Design (6)
Distributed Resource Management (6)
Electronic Hardware (6)
FPU (6)
Fabric (6)
Front and Back Door (6)
HDM (6)
Hierarchical Flow (6)
High-Speed (6)
IP Integration (6)
June 2019 - Volume 15 Issue 2 (6)
MARLUG 2023 (6)
MBIST (6)
MIPI (6)
March 2014 - Volume 10 Issue 1 (6)
March 2017 - Volume 13 Issue 1 (6)
March 2020 - Volume 16 Issue 1 (6)
March 2024 - Volume 20 Issue 1 (6)
Metric Validation (6)
November 2016 - Volume 12 Issue 3 (6)
November 2020 - Volume 16 Issue 3 (6)
October 2012 - Volume 8 Issue 3 (6)
October 2013 - Volume 9 Issue 3 (6)
Open Source (6)
Power Efficiency (6)
Pre-Silicon (6)
Random Faults (6)
Respins (6)
Secure Data Path (6)
Slave (6)
Static & Formal Adoption (6)
Transaction-Level (6)
UVM Forum (6)
UVVM (6)
VA Live 2024 - El Segundo (6)
VA Live 2024 - San Diego (6)
VA Live 2025 - El Segundo (6)
VA Live 2025 - Hudson (6)
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VHDL Testbench (6)
Verbosity (6)
Verification Complete (6)
Verification Effectiveness (6)
Visualization (6)
Windows (6)
X-Effects (6)
YAML (6)
osmosis 2024 A&D (6)
ATPG (5)
Advance Your Verification Methodology (5)
Agile Development (5)
Analysis Pattern (5)
BIST (5)
Base Class (5)
Bug Detection (5)
Bus Functional Models (5)
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CHERI (5)
Callbacks (5)
Class Library (5)
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Clock Propagation (5)
Co-Verification (5)
Concurrent Processes (5)
Constraint Solver (5)
Converters (5)
Coverage Holes (5)
DAC 2024 (5)
DSP (5)
Debug Methodology (5)
December 2019 - Volume 15 Issue 3 (5)
Defect Coverage (5)
Design Scaling (5)
Dual Domains (5)
Error (5)
FMEDA (5)
February 2019 - Volume 15 Issue 1 (5)
Flip-Flop (5)
Formal Testbench (5)
HBM4 (5)
Hierarchical Data Model (5)
Implicit/Explicit (5)
In-Circuit Emulation (5)
JEDEC (5)
Low Power Verification Forum (5)
MARLUG 2024 (5)
MARLUG 2025 (5)
March 2018 - Volume 14 Issue 1 (5)
NVM Express (5)
Namespaces (5)
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Processor Core Verification (5)
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Quirky (5)
Repository (5)
SSD (5)
SVUnit (5)
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Simulink (5)
Spice (5)
Split Transactor (5)
State-Based Model (5)
Static Analyses (5)
Static RDC (5)
Stimulus Pattern (5)
Test Class (5)
Threads (5)
Transaction-Based Acceleration (5)
UCIe 3.0 (5)
VA Live 2019 - Westford (5)
VA Live 2023 - Westford (5)
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VA Live 2024 - Westford (5)
VA Live 2025 - Silicon Valley (5)
Verbose (5)
Virtual Methods (5)
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5G (4)
AI Model (4)
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Batch and Debug (4)
Bi-Directional (4)
Bins (4)
Bit Width (4)
Black Boxing (4)
C++ (4)
CXL (4)
Corner-case Bugs (4)
Coverage Achievement (4)
Data Encryption (4)
Data Link (4)
Deprecated (4)
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Design Constraints (4)
Determinism (4)
Digital Twin (4)
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Dynamic Power (4)
ECO (4)
ED-80 (4)
Enumeration (4)
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Floating-Point Units (4)
Formal Closure (4)
Formal Methods (4)
HBM (4)
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ICE Mode (4)
IEEE (4)
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LFM (4)
Large Language Models (4)
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Metastability Injection (4)
Mitigation Architecture (4)
Non-Pipelined (4)
Non-Reset (4)
November 2018 - Volume 14 Issue 3 (4)
PCIe Gen 6 (4)
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Phase Objections (4)
Phases (4)
Plusargs (4)
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Protocol Checkers (4)
QoR (4)
Questa Design Solutions (4)
Race Conditions (4)
Register-Level Scoreboards (4)
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Reset Signal (4)
Root Cause (4)
SVTB (4)
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Subscriber (4)
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Tcl/Tk (4)
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UART (4)
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USB (4)
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VA Live 2023 - Austin (4)
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Verification Models (4)
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X-Aware (4)
$display (3)
1.2 (3)
AHB (3)
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Airborne Electronic Hardware (3)
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Golden Model (3)
HDL (3)
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July 2023 - Volume 19 Issue 2 (3)
Jump Statements (3)
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UVM 1.1d (3)
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