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UVM Simulation of MathWorks® Designs at Block, Subsystem, and Chip Level

Webinar - Aug 05, 2021 by Pedram Riahi - Raytheon

This session is a customer presentation on his experience using the UVMF and Mathworks® integration in block, subsystem, and chip level simulations.
Deploying Formal in a DO-254 Program

Resource (Verification Horizons Blog) - Aug 02, 2021 by Jake Wiltgen

The primary focus of DO-254, referred to as ED-80 in Europe, is hardware reliability of airborne electronic hardware. DO-254 is considered state of the art and compliance is compulsory for any company putting an IC on an aircraft. One component of the standard is the verification of functional behavior.
Managing Requirements in a Functional Safety Environment

Webinar - Jul 29, 2021 by Thorsten Stahlberg - Siemens EDA

In this session, you will learn that Requirements Management in a "Functional Safety" environment can be very challenging. With Polarion ALM you have a comprehensive solution at hand that fully supports you in successfully managing not only the pure requirements themselves but also all related processes.
Using Formal Verification in Daily Work

Webinar - Jul 29, 2021 by Dr. Abdelouahab Ayari - Siemens EDA

In this session, we will describe some typical formal applications and how the formal results can be integrated with other verification results.
Digital Functional Verification for Safety-Critical Automotive Applications

Webinar - Jul 29, 2021 by Michael Bierl - Siemens EDA

In this session, you will be shown a coverage driven verification flow based on the Questa platform. You will also learn how a web-based platform helps to finalize the project successfully even in teams spread over multiple locations.
CDC Verification: Beyond Structural Analysis

Webinar - Jul 29, 2021 by Mark Handover

In this session, we will cover the overall CDC methodology and cover CDC protocols and reconvergence in more details and show what could happen if these steps are skipped.
Mitigating the Effects of Random Hardware Faults

Webinar - Jul 29, 2021 by Dirk Hansen

Random faults cannot be prevented so the goal there is to sufficiently tolerate them. With random faults you are really just trying to make sure that the product will fail safely when inevitably one of these random hardware faults occurs. In this session we will outline approaches on how to tackle systematic as well as random faults.
AMS Functional Verification for Safety-Critical Automotive Applications

Webinar - Jul 29, 2021 by Sumit Vishwakarma

In this session, you will learn how Siemens EDA Symphony platform addresses today's nanometer mixed signal verification challenges for safety-critical automotive applications.
A Path to Develop Safe ICs - Part 2

Webinar - Jul 29, 2021 by Stephanie Dournelle, Paul Williams - Siemens EDA

In this session you will learn that Siemens EDA has developed a platform that allows early collaboration between OEMs and their suppliers. It provides a clear definition of requirements and allows hardware and software functionality to be tested in a virtual environment long before silicon is available.
A Path to Develop Safe ICs - Part 1

Webinar - Jul 29, 2021 by Stephanie Dournelle - Siemens EDA

In this session, you will learn that Siemens EDA helps customers adapt to the required development flows, develop safety collateral for their designs, and mitigate the risk of product failure in safety critical applications.
Extending the Role of Test and In-System Test to Meet Automotive Safety and Security Requirements

Webinar - Jul 29, 2021 by Lee Harrison

In this session, we will show how Design For Test is expanding from its traditional role into one that includes the management of the entire silicon lifecycle, to become Silicon Lifecycle Solutions. Ensuring that ICs work safely as expected and are secure throughout their operational life.
Hardware-Accelerated & Software-Driven Verification

Webinar - Jul 29, 2021 by Ajay Sharma

In this session we will talk about ease of adopting Emulation and various ways of using the powerful Apps that bring in software to improve accuracy of verification process.
Automotive SOTIF Compliance for Arm with PAVE360

Webinar - Jul 29, 2021 by Antonio Priore - Arm, Joe Dailey - Siemens, Tapan Vikas - Siemens EDA

In this session, we will explain Safety Of The Intended Function (SOTIF) and demonstrate techniques to prove systems.
Are Random Hardware Faults Common?

Webinar - Jul 29, 2021 by Dirk Hansen

In this session, you will be given an introduction of solutions to analysis failure modes resulting from random hardware faults. These can guide the user to unsafe areas of the design where safety mechanisms need to be inserted.
Traceability for Automotive Standards Compliance

Webinar - Jul 29, 2021 by Darron May

In this session, you will learn how the combination of Siemens Polarion ALM Requirements Management and Questa Verification Management solve the lifecycle management and traceability requirements for Automotive projects.
The Future of Automotive and its Impact on Safety

Session - Jul 29, 2021 by Ann Keffer

This session will provide a perspective on the impact to companies developing automotive ICs and serves as the introduction to the multi-part automotive safety webinar series covering many aspects of an automotive safety lifecycle.
It’s Not My Fault! How to Run a Better Fault Campaign Using Formal

Resource (Paper (.PDF)) - Jul 21, 2021 by Doug Smith

The ISO 26262 automotive safety standard requires evaluation of safety goal violations due to random hardware faults to determine diagnostic coverages (DC) for calculating safety metrics. Injecting faults using simulation may be time-consuming, tedious, and may not activate the design in a way to propagate the faults for testing.
Part II: Verification of PCIe® IP

Webinar - Jul 15, 2021 by Stephane Hauradou

In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.
UVM Framework Release 2021.3

Resource (Tarball) - Jul 13, 2021 by Bob Oden

General Updates: General bug fixes and documentation updates Generator Updates: Added C data types for Mathworks® integration flow
Sequential Logic Equivalence Checking

Track - Jul 06, 2021 by Jin Hou

In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.
SLEC Introduction

Session - Jul 06, 2021 by Jin Hou

In this session, you will learn the concept of sequential logic equivalence checking (SLEC) and the common applications of SLEC.
SLEC for Design Optimization

Session - Jul 06, 2021 by Jin Hou

In this session, you will learn how to use SLEC to verify functional equivalence between two RTL designs before and after optimization.
SLEC for Bug Fix / ECO

Session - Jul 06, 2021 by Jin Hou

In this session, you will learn how to use SLEC to verify that bug fix/ ECO doesn’t introduce new bugs.
SLEC for Low Power Clock Gating

Session - Jul 06, 2021 by Jin Hou

In this session, you will how to use SLEC to verify that the design works the same with and without added low power clock gating logic.
SLEC for Safety Mechanism

Session - Jul 06, 2021 by Jin Hou

In this session, you will learn how to use SLEC to verify that the design’s safety mechanism handles faults as required.