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• A Formal-based Approach for Efficient RISC-V Processor Verification

  Article - Feb 24, 2023 by Laurent Arditi, Paul Sargent, Thomas Aird, Lauranne Choquin - Codasip

  The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also shifting the verification responsibility to a growing community of developers. Processor verification, however, is never easy. The very novelty and flexibility of the new specification results in new functionality that inadvertently creates specification and design bugs.

• Effective Validation Method of Safety Mechanism Compliant with ISO 26262

  Article - Jul 19, 2020 by Toshiyuki Hamatani - Verification Technology, Inc.

  The metrics to measure the effectiveness of Safety Mechanisms include code coverage rate, SPFM (Single- point failure metric) and LFM (Latent failure metric). Especially in SPFM and LFM, if the specified value is not reached on the Fault Injection Simulation (using Gate Level) at the end of verification, it will cause iterations, which will cause a significant increase in time and cost compared to consumer LSIs.

• Part 2: Power Aware Static Verification – From Power Intent to Microarchitectural Checks of Low-Power Designs

  Article - Jun 29, 2018 by Progyna Khondkar

  Part I of this article provided a consolidated approach to understand verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requirements, statically on the structures of the design.

• The RISC-V Verification Interface (RVVI) – Test Infrastructure and Methodology Guidelines

  Article - Feb 24, 2023 by Aimee Sutton, Lee Moore, Kevin McDermott - Imperas Software

  The open standard ISA of RISC-V is at the forefront of a new wave of design innovation. The flexibility to configure and optimize a processor for the unique target application requirements has a lot of appeal in emerging and established markets alike. RISC-V can address the full range of compute requirements such as an entry-level microcontroller, a support processor, right up to the state-of-the-art processor arrays with vector extensions for advanced AI applications and HPC.

• Automation and Reuse in RISC-V Verification Flow

  Article - Jun 28, 2017 by Marcela Zachariasova, Lubos Moravec - Codasip, Ltd.

  The Open RISC-V Instruction Set Architecture (ISA) managed by the RISC-V foundation 1 and backed by an ever increasing number of the who's who in the semiconductor and systems world, provides an alternative to legacy proprietary ISA's. It delivers a high level of flexibility to allow development of very effective application optimized processors, which are targeted to domains that require high performance, low area or low power.

• Simulation

  Topic - by Moses Satyasekaran

  Simulation plays a pivotal role in the digital design and verification process. Its primary purpose is to validate whether the design being created functions according to the specified requirements. By running simulations early in the design phase, potential issues can be identified, thus minimizing the need for extensive code revisions. Simulations can be performed at different levels of abstraction and at various stages throughout the design process.

• Questa CDC-FX: Metastability Effects Delay Modeling

  Paper - Jun 28, 2024 by Kurt Takara

  In this paper, we survey traditional metastability effect models and discuss the shortcomings of each of them. We then present the model used by Questa CDC-FX, from Siemens EDA, and describe why it is a more accurate and complete metastability-effects model.

• Three Steps to Unified SoC Design and Verification

  Article - Aug 19, 2016 by Mark Peryer

  Developing a SoC is a risky business in terms of getting it right considering the technical complexity involved, managing the mixture of hardware and software design disciplines, and finding an optimal trade-off between design performance and power. One way to reduce these risks is to use a design and verification flow that is scalable enough to handle the complexity and is flexible enough to explore architectural alternatives early in the design cycle before implementation starts.

• Monitors, Monitors Everywhere – Who Is Monitoring the Monitors

  Article - Jun 01, 2013 by Rich Edelman

  The reader of this article should be interested in predicting or monitoring the behavior of his hardware. This article will review phase-level monitoring, transaction-level monitoring, general monitoring, in-order and out-of-order transaction-level monitors, A protocol specific AXI monitor written at the transaction-level of abstraction will be demonstrated. Under certain AXI usages, problems arise.

• First Time Unit Testing Experience Report with SVUnit

  Article - Mar 02, 2016 by Neil Johnson

  Verification teams don’t typically verify testbench components. But this Qualcomm Technologies IP team realized the necessity of unit testing a critical testbench component and the corresponding debug time and frustration it could prevent for downstream IP and chip teams.

• Memory Softmodels - The Foundation of Validation Accuracy

  Article - Oct 26, 2020 by Ridham Kothari - Siemens EDA

  As always, we must continue to reduce the time-to-market of SoCs and complex systems. An FPGA prototype implementation of these systems can be used as a basis for early software or firmware development, hardware-software co-verification and system validation, and all this can be achieved before actual silicon is available.

• Best Practices for FPGA and ASIC Development

  Article - Jun 16, 2014 by Josh Rensch, John Boone - Siemens EDA

  This is an overview of best practices for FPGA or ASIC design, assuming a traditional waterfall development process. There are four development phases: PLAN, EXECUTE, VERIFY and SUPPORT. A review step is recommended between each phase, as prescribed by DO-254. These concepts can be used in alternative methodologies, like Agile.

• "Hug the Debug" – Before It’s Too Late

  Article - Sep 01, 2021 by Sumit Vishwakarma

  Though the term “shift-left” originated in the software industry, its importance is often cited in the hardware (semiconductor) industry where the end-product (chip) costs are skyrocketing. The increase in cost is driven by the global chip shortage, especially in the automotive industry.

• Enabling Model-Based Design for DO-254 Certification Compliance

  Article - Mar 02, 2022 by Jake Wiltgen

  Engineers can use Model-Based Design for requirements analysis, algorithm design, automatic HDL code generation, and verification to produce airborne electronic hardware that adheres to the DO-254 standard. The proposed Model-Based Design approach for DO-254 combines tools from MathWorks® and Siemens EDA for both design and verification. This workflow supports development phases from concept through implementation, streamlining development, and reducing costs.

• RISC-V Design Verification Strategy

  Article - Oct 26, 2020 by Dr. Mike Bartley

  As the RISC-V architecture becomes increasingly popular, it is being adopted across a diverse range of products. From the development of in-house cores with specialized instructions, to functionally safe SoCs and security processors for a variety of verticals – RISC-V adoption brings several verification challenges that are discussed in this article, along with potential approaches and solutions.

• The Democratization of Digital Methodologies for AMS Verification

  Article - Jul 05, 2022 by Sumit Vishwakarma

  A mixed-signal design is a combination of tightly interlaced analog and digital circuitry. Next-generation automotive, imaging, IoT, 5G, computing, and storage markets are driving the strong demand for increasing mixed-signal content in modern systems on chips (SoCs). There are two critical reasons for this trend.

• What Siemens’ Acquisition of OneSpin Means for Formal Verification – and You

  Article - Sep 01, 2021 by Tom Fitzpatrick

  Preface: in May 2021 Siemens EDA acquired OneSpin Solutions, combining Siemens' Questa Formal products and expertise (with roots and team members from 0-In) with OneSpin’s “apps first” approach to key growth markets including Trust&Security, Safety, RISC-V, and FPGAs. The combination adds to a cohesive Siemens EDA verification solution spanning simulation, formal, emulation, and prototyping.

• Verification Cookbook Glossary

  Chapter - Mar 31, 2014 by Verification Methodology Team

  This page is an index to the glossary of various terms defined and used in the Cookbook.

• Robustness Verification of ARINC708’s Manchester Codes in a DO-254 Project

  Article - Jun 21, 2023 by Emin Akgün, Hilal Güneren - ANKASYS

  In this article, we will discuss the Display Data Bus of ARINC-708. The bus plays a critical role in terms of the pilot’s point of view. It requires a bi-phase Manchester encoding and decoding. For both Manchester coding and the bus protocol, some examples of possible error types are considered.

• Hardware-Assisted Verification Through the Years

  Article - Sep 01, 2021 by Jean-Marie Brunet

  A quick glance in today’s design verification toolbox reveals a variety of point tools supporting the latest system-on-chip (SoC) design development. When combined and reinforced by effective verification methodologies, these tools trace even the most hard-to-find bug, whether in software or in hardware. The focus on tools and delivering a tightly woven integration between complementary tools is a strategic focus at Siemens EDA.

• Celebrating 10 Years of the UVM

  Article - Mar 03, 2021 by Mark Peryer

  Version 1.0 of the UVM class library was released by Accellera at the end of February 2011, the result of a unique collaborative effort between fierce competitors (Siemens EDA, formerly Mentor Graphics, Cadence, and Synopsys) and a small number of activist user companies. The objective was to provide an industry standard SystemVerilog based verification methodology.

• Smoothing the Path to Software-Driven Verification with Portable Stimulus

  Article - Jun 28, 2017 by Matthew Ballance

  Designs are becoming more complex and increasingly include a processor – and often multiple processors. Because the processor is an integral part of the design, it's important to verify the interactions between software running on the processor and the rest of the design.

• On-Chip Debug – Reducing Overall ASIC Development Schedule Risk

  Article - Nov 01, 2015 by Eric Rentschler - Siemens EDA

  With ASIC complexity on the increase and unrelenting time-to-market pressure, many silicon design teams still face serious schedule risk from unplanned spins and long post-silicon debug cycles. However, there are opportunities on both the pre-silicon and post-silicon sides that can be systematically improved using on-chip debug solutions.

• Is Intelligent Testbench Automation For You?

  Article - Sep 02, 2015 by Mark Olen

  Intelligent Testbench Automation (iTBA) is being successfully adopted by more verification teams every day. There have been multiple technical papers demonstrating successful verification applications and panel sessions comparing the merits to both Constrained Random Testing (CRT) and Directed Testing (DT) methods. Technical conferences including DAC, DVCon, and others have joined those interested in better understanding this new technology.

• Evolving the Use of Formal Model Checking in SoC Design Verification

  Article - Mar 11, 2015 by Ram Narayan

  Project RAPID is a hardware-software co-design initiative in Oracle Labs that uses a heterogeneous hardware architecture combined with architecture-conscious software to improve the energy efficiency of database-processing systems.