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102 Results

Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive

Article - Sep 01, 2021 Jean-Marie Brunet

Despite abundant rumors predicting the end of life for Moore’s Law (the axiom stating transistor density doubles every 24 months), semiconductor design sizes continue to grow exponentially with no end in sight. In the process, design sizes push costs off the roof. According to market research International Business Strategies (IBS), the total cost of designing a state-of-the-art system on chip (SoC) at the 5nm process technology node exceeds half a billion dollars.
DFT's Expanding Role in Software-Driven Silicon: From Structural Test Closure to System-Assurance Evidence

Session - Sep 08, 2026 Harry Foster

This video explores the key findings from the DFT's Expanding Role in Software-Driven Silicon white paper, which provides a snapshot of current industry practices rather than a longitudinal trend analysis. While many of the individual techniques and workflows highlighted in the study are well established, the results quantify their adoption within a common industry framework and reveal how they are increasingly converging.
DFT's Expanding Role in Software-Driven Silicon: From Structural Test Closure to System-Assurance Evidence

Paper - Sep 08, 2026 Harry Foster

Examine the earlier verification of design-for-test logic, integration between DFT and functional verification, accelerated execution, and evolving ownership across engineering teams.
Standardization of HDMs for Hierarchical CDC and RDC Analysis

Paper - Oct 01, 2025 Farhad Ahmed

Currently HDMs must be generated with the same EDA tool that customers will use to consume the HDM for CDC and RDC analysis at the SoC level. To resolve this problem a CDC Working Group was created within the Accellera organization. The goal of this Working Group is to create a standard format for HDMs so the models can be consumed by any EDA tool irrespective of the source of the generated model.
Deploying HLS in a DO-254/ED-80 Workflow

Article - Sep 01, 2021 Tammy Reeve - Patmos Engineering Services

The adoption of tools into safety-critical workflows is often challenging as these new technologies must demonstrate sufficient safeness to use before being deployed in production environments. The demand for High-Level Synthesis capabilities within DO-254 projects is growing and this paper describes the requirements and considerations to successfully use High-Level Synthesis within a DO-254 workflow.
Introduction to the Verification Academy

Session - Feb 25, 2011 Harry Foster

This session provides a common framework for all advanced functional verification tracks contained within the Verification Academy.
Verify Thy Verifyer

Article - Mar 01, 2020 Srinivasan Venkataramanan, Ajeetha Kumari - VerifWorks

Design Verification is a field that requires a lot of thinking and equally a lot of coding. Tighter time-to-market adds a lot of schedule pressure to the teams coding those testbenches and test cases. The advent of UVM (Universal Verification Methodology) as the standard framework, has helped the industry make good progress in terms of structured testbenches. One of the primary objectives of UVM is to build robust, reusable testbenches.
Machine Learning

Topic

Machine learning (ML) has emerged as a powerful tool in the field of verification engineering, revolutionizing the way we validate and verify complex systems. Verification engineers are responsible for ensuring that hardware and software systems meet their specifications and perform reliably. In this context, machine learning offers a fresh approach to address challenges and enhance the verification process.
Delivering First Silicon Success for Your Next SoC or 3DIC

Webinar - Apr 25, 2023 Gordon Allan

In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.
System Level Functional Coverage Example

Chapter - Dec 04, 2013 Harry Foster

System level functional verification can take full advantage of the fact that the entire design is a self-contained unit that will be used by customers and thus has some logical use model that the customer will follow. Also, being a system, often it is made up of trusted IP, and the verification focus is aimed more at the block interconnect and any new functionality. Working at a system level, leads to the creation of a coherent coverage model spreadsheet/test plan using the top-down method .
Equivalence Checking for FPGA

Webinar - Jul 06, 2021 Martin Rowe

In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.
Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs

Webinar - Sep 30, 2022 Martin Rowe

In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.
Simulation

Topic

Simulation plays a pivotal role in the digital design and verification process. Its primary purpose is to validate whether the design being created functions according to the specified requirements. By running simulations early in the design phase, potential issues can be identified, thus minimizing the need for extensive code revisions. Simulations can be performed at different levels of abstraction and at various stages throughout the design process.
QVIP Provides Thoroughness in Verification

Article - Nov 01, 2015 Kiran Sharma, Vipin Kumar - Agnisys Technology Pvt. Ltd.

The present day designs use standard interfaces for the connection and management of functional blocks in System on Chips (SoCs). These interface protocols are so complex that, creating in-house VIPs could take a lot of engineer’s development time. A fully verified interface should include all the complex protocol compliance checking, generation and application of different test case scenarios, etc.
FPGA Verification

Topic

FPGA (Field-Programmable Gate Array) verification, including methods like simulation and formal verification, is invaluable for ironing out design issues before deploying hardware in the lab. Simulation allows engineers to comprehensively test the FPGA design under various conditions, helping detect and rectify potential bugs and ensuring functionality. By conducting thorough FPGA verification, costly and time-consuming hardware iterations are minimized, significantly reducing the risk of errors and shortening the time-to-lab phase. This approach ultimately leads to more efficient development, lower expenses, and a faster path to achieving operational hardware.
A Formal-based Approach for Efficient RISC-V Processor Verification

Article - Feb 24, 2023 Laurent Arditi, Paul Sargent, Thomas Aird, Lauranne Choquin - Codasip

The openness of RISC-V allows customizing and extending the architecture and microarchitecture of a RISC-V based core to meet specific requirements. This appetite for more design freedom is also shifting the verification responsibility to a growing community of developers. Processor verification, however, is never easy. The very novelty and flexibility of the new specification results in new functionality that inadvertently creates specification and design bugs.
Three Steps to Unified SoC Design and Verification

Article - Oct 01, 2012 Mark Peryer

Developing a SoC is a risky business in terms of getting it right considering the technical complexity involved, managing the mixture of hardware and software design disciplines, and finding an optimal trade-off between design performance and power. One way to reduce these risks is to use a design and verification flow that is scalable enough to handle the complexity and is flexible enough to explore architectural alternatives early in the design cycle before implementation starts.
Close Coverage Faster with Questa One Sim's Unreachability Analysis

Webinar - Feb 05, 2026 Justin Royse

Coverage closure remains the single largest challenge facing functional verification teams today, affecting 34% of both ASIC and FPGA design projects. As verification approaches completion, coverage scores plateau well short of project goals—a phenomenon commonly known as the "Last Mile problem." This webinar explores why traditional approaches to closing coverage gaps fall short and introduces  automated unreachability analysis  in Questa One Sim as a transformative solution.
Effective Validation Method of Safety Mechanism Compliant with ISO 26262

Article - Jul 19, 2020 Toshiyuki Hamatani - Verification Technology, Inc.

The metrics to measure the effectiveness of Safety Mechanisms include code coverage rate, SPFM (Single- point failure metric) and LFM (Latent failure metric). Especially in SPFM and LFM, if the specified value is not reached on the Fault Injection Simulation (using Gate Level) at the end of verification, it will cause iterations, which will cause a significant increase in time and cost compared to consumer LSIs.
Power Aware Static Verification: From Power Intent to Microarchitectural Checks of Low Power Designs - Part 2

Article - Jun 29, 2018 Progyna Khondkar

Part I of this article provided a consolidated approach to understand verification tools and methodologies that applies a set of pre-defined power aware (PA) or multi-voltage (MV) rules based on the power requirements, statically on the structures of the design.
The RISC-V Verification Interface (RVVI) – Test Infrastructure and Methodology Guidelines

Article - Feb 24, 2023 Aimee Sutton, Lee Moore, Kevin McDermott - Imperas Software

The open standard ISA of RISC-V is at the forefront of a new wave of design innovation. The flexibility to configure and optimize a processor for the unique target application requirements has a lot of appeal in emerging and established markets alike. RISC-V can address the full range of compute requirements such as an entry-level microcontroller, a support processor, right up to the state-of-the-art processor arrays with vector extensions for advanced AI applications and HPC.
Automation and Reuse in RISC-V Verification Flow

Article - Jun 28, 2017 Marcela Zachariasova, Lubos Moravec - Codasip, Ltd.

The Open RISC-V Instruction Set Architecture (ISA) managed by the RISC-V foundation 1 and backed by an ever increasing number of the who's who in the semiconductor and systems world, provides an alternative to legacy proprietary ISA's. It delivers a high level of flexibility to allow development of very effective application optimized processors, which are targeted to domains that require high performance, low area or low power.
Questa CDC-FX: Metastability Effects Delay Modeling

Paper - Jun 28, 2024 Kurt Takara

In this paper, we survey traditional metastability effect models and discuss the shortcomings of each of them. We then present the model used by Questa CDC-FX, from Siemens EDA, and describe why it is a more accurate and complete metastability-effects model.
Monitors, Monitors Everywhere: Who is Monitoring the Monitors

Article - Jun 01, 2013 Rich Edelman

This article will review phase-level monitoring, transaction-level monitoring, general monitoring, in-order and out-of-order transaction-level monitors, A protocol specific AXI monitor written at the transaction-level of abstraction will be demonstrated. Under certain AXI usages, problems arise.
First Time Unit Testing Experience Report with SVUnit

Article - Mar 02, 2016 Neil Johnson

Verification teams don’t typically verify testbench components. But this Qualcomm Technologies IP team realized the necessity of unit testing a critical testbench component and the corresponding debug time and frustration it could prevent for downstream IP and chip teams.