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Simulating CDC Reconvergence: Validating Robustness with Questa One Sim's Metastability Injection
Resource (Slides (.PDF)) - Jan 21, 2026 by Sunil Sahoo
In this webinar, you will learn how to gain unparalleled confidence in your design’s resilience to metastability effects, ensuring robust functional correctness and accelerating verification closure for complex multi-clock SoCs.
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Episode 3: Chandu Challapalli
Resource (Podcast) - Jan 20, 2026 by Harry Foster
Harry Foster talks with Chandu Challapalli, Senior Management Director at Siemens EDA, about why timing constraints must be treated as first-class verification assets. Drawing on insights from his white paper, A Guide to SDC-based Timing Intent Verification with Questa One , Chandu explains how automated SDC verification uncovers hidden timing risks, balances under- and over-constraining, and shifts timing validation earlier in the design cycle.
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New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity
Resource (Paper (.PDF)) - Jan 16, 2026 by Jin Hou
The heterogeneous integration of multiple ICs in a single package along with high-performance, high bandwidth memory is critical for many high-performance computing applications. After everything has been heterogeneously integrated and packaged, such designs feature complex connectivity with many hundreds of thousands of connections, making it extremely challenging to verify the correctness of the connections.
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New Innovative Way to Functionally Verify Heterogeneous 2D/3D Package Connectivity
Paper - Jan 16, 2026 by Jin Hou
This paper introduces a new way to functionally verify packaging connectivity using formal verification that can exhaustively verify all interconnections between IC blocks. The flow is automatic for all steps, from creating connectivity specifications to verifying packaging output connectivity. The automatic parallel algorithms on the compute grid can verify huge numbers of connections in minutes or even seconds. The script for the flow is simple and only takes a few minutes to set up.
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Formal Verification Made Simple: A Practical Guide for FPGA Designers
Webinar - Jan 15, 2026 by Bobana Brzacki
In this webinar we will demystify formal verification and show you how SFV fits naturally into your existing FPGA design flow. Whether you're working on control logic, interfaces, or complex state machines, you'll discover how formal can catch bugs that simulation misses - early, automatically, and exhaustively.
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Formal Verification Made Simple: A Practical Guide for FPGA Designers
Resource (Slides (.PDF)) - Jan 15, 2026 by Bobana Brzacki
If you're an FPGA designer who's heard that formal verification is "too complex" or "not for FPGA workflows," this session will change your mind.
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Constrained Randomization and Functional Coverage in Questa One Sim with UVVM
Webinar - Jan 14, 2026 by Abdelrahman Tharwat
In this webinar, we’re excited to showcase the latest cutting-edge features of Questa One Sim, with UVVM (Universal VHDL Verification Methodology) . Learn how the newly added support for constrained randomization with multi-variable capabilities allows you to dynamically generate randomized, UVVM-compliant stimuli that address even the most intricate design constraints, helping you explore vast verification scenarios efficiently and effectively.
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Constrained Randomization and Functional Coverage in Questa One Sim with UVVM
Resource (Slides (.PDF)) - Jan 14, 2026 by Abdelrahman Tharwat
This webinar is your gateway to unlocking a streamlined and enhanced verification experience by leveraging Questa One Sim advanced features in tandem with UVVM.
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System Verifier
Resource (Verification Horizons Blog) - Jan 05, 2026 by Julie Weber
Software-defined, AI-controlled systems are transforming industries—from aerospace and defense to automotive and industrial automation. But with this transformation comes complexity: as software workloads grow, electronic systems face higher risks of non-deterministic failure mechanisms. Traditional engineering methods and tools are no longer enough to anticipate these risks or prevent “integration hell.”
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FutureCast 2026: Part 2
Resource (Podcast) - Dec 16, 2025 by Harry Foster
Harry Foster returns with Part 2 of this special holiday edition of BUGGED OUT , continuing the exploration of how silicon and verification are rapidly evolving. In this episode, Harry looks at the forces accelerating change — from rising specialization and data-movement bottlenecks to growing power and security pressures that now shape system behavior. To dive deeper into these themes, you can also download the companion paper — The Future of Semiconductors: Engineering in the Convergence Era .
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Formal Verification of Synthesizable C++/SystemC Designs
Resource (Paper (.PDF)) - Dec 12, 2025 by Vlada Kalinic
In this paper, you will learn that HLV formal tools from Siemens can be used to clean SystemC/C++ design code before running HLS as well as to verify the functionality of the SystemC designs with SVA assertions. Steps in this flow include using the GUI counter-example capability to debug failures on the SystemC/C++ designs and focusing on the reachable parts by using the increase coverage solution to detect unreachable code.
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Formal Verification of Synthesizable C++/SystemC Designs
Paper - Dec 12, 2025 by Vlada Kalinic
Formally checking generated RTL can be difficult to analyze as errors cannot be correlated to the HLS source code. Questa HLV can help overcome this challenge with high-level verification. Siemens offers several apps to verify and clean C++ HLS code before running HLS and then check the equivalency between C++ and RTL.
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The Future of Semiconductors: Engineering in the Convergence Era
Resource (Paper (.PDF)) - Dec 09, 2025 by Harry Foster
The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade.
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The Future of Semiconductors: Engineering in the Convergence Era
Paper - Dec 09, 2025 by Harry Foster
Reflections from inside an industry undergoing its biggest transformation in decades. The semiconductor industry is entering a convergence era where silicon, software, physics, packaging, security, AI, and power constraints all intertwine. Device scaling still matters but architecture, integration, verification, and automation will define the industry’s trajectory. Organizations that embrace this cross-domain, lifecycle-oriented mindset will define the next decade.
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FutureCast 2026: A Special Holiday Edition of BUGGED OUT
Resource (Verification Horizons Blog) - Dec 09, 2025 by Harry Foster
As another year closes, the semiconductor industry finds itself in a moment of transition—one where the pace of innovation is accelerating faster than many expected. Chip architectures are evolving, system boundaries are shifting, and verification continues expanding into new territory we couldn’t have imagined even a decade ago. And like many of you, I find the end of the year to be a natural time to pause, look back, and ask a simple but important question: Where is all of this heading?
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FutureCast 2026: Part 1
Resource (Podcast) - Dec 04, 2025 by Harry Foster
Harry Foster kicks off a special two-part holiday edition of BUGGED OUT with a look at the rapidly shifting landscape of modern silicon. Harry also shares his predictions for where the semiconductor and verification ecosystem is headed in 2026 — and beyond. To dive deeper into these themes, you can also download the companion white paper— The Future of Semiconductors: Engineering in the Convergence Era .
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Aerospace & Defense
Reference - Dec 03, 2025 by Todd Holbrook
Welcome to the Aerospace and Defense event archive, where you will find presentations and slide decks from live events that you may have missed. *Please note: you will need a valid login to download the session presentations.
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Questa One Smart Verification: Unleashing the Potential of AI Within Functional Verification
Resource (Slides (.PDF)) - Dec 03, 2025 by Austin Mam
Leverage the power of AI and ML Smart Verification revolutionizes functional verification by using faster engines that complement traditional heuristics with machine learning. Allow engineers to be more productive with advanced creation, analysis, and debugging capabilities, while reducing workloads through predictive technologies that streamline and accelerate the verification process.
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Introducing Questa One SFV: The Transformation of Static & Formal Powered by AI/ML
Resource (Slides (.PDF)) - Dec 03, 2025 by David Landoll
In today's fast-paced development schedules, engineers are constantly balancing innovation with efficiency. Questa One SFV, powered by AI/ML, is designed to streamline workflows, eliminate steep learning curves, and accelerate adoption. Learn how SFV can integrate into your current flow and improve productivity.
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Ensure High Quality RTL with Early Continuous Integration
Resource (Slides (.PDF)) - Dec 03, 2025 by Walter Gude
Learn the value of Continuous Integration (CI) during development and how Questa Design Solutions are ideally suited for implementation in CI flows. Discover the benefits of integrating CI early to enhance RTL quality and streamline development processes.
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Enhancing Verification Productivity with Questa One
Resource (Slides (.PDF)) - Dec 03, 2025 by Sunil Sahoo
Improving productivity has become crucial for efficiently utilizing expensive human and grid resources in the functional verification process. Achieving the "done" state requires more than simulator performance— it demands a strategic focus on optimizing workflows, prioritizing tasks, and leveraging metrics to guide efforts. Questa One Sim's productivity-driven approach ensures resources are deployed effectively, accelerating verification closure.
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VA Live - Scottsdale: Introduction and Welcome
Resource (Slides (.PDF)) - Dec 03, 2025 by Todd Holbrook
Welcome to Verification Academy Live.
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Debug Like a Pro: VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim
Webinar - Dec 03, 2025 by Mariam Maurice
This webinar explores the debugging capabilities and best practices across the three leading VHDL verification (OSVVM, UVVM, UVM) frameworks.
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Debug Like a Pro: VHDL Testbenches with OSVVM, UVVM, & UVM in Questa One Sim
Resource (Slides (.PDF)) - Dec 03, 2025 by Mariam Maurice
This webinar explores the debugging capabilities and best practices across these three leading VHDL verification frameworks.
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Accelerating Coverage Closure in FPGA Verification: Metric-Driven Verification Leveraging Questa CoverCheck
Resource (Slides (.PDF)) - Nov 19, 2025 by Ajay Bhaskaran - L3Harris
In this session, you will learn how FPGAs have evolved to match ASIC-level complexity, there is a dire need for deploying metric-driven verification to ensure comprehensive verification with the need for “accelerated” coverage closure. We share key challenges, and deployment steps from implementing Questa CoverCheck for automated Code coverage analysis and improvement, highlighting measurable gains in verification execution efficiency with tangible results.