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The UVM Factory Revealed - Part 1
Resource (Verification Horizons Blog) - Jan 20, 2023 by Chris Spear
When you first learn UVM, most of the concepts make sense, even if you are new to Object-Oriented Programming. Except one, the UVM Factory. Why do you need all that extra code, class::type_id::create(), just to make an object? What’s wrong with just calling new()? The answer is teamwork!
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Does Your UVM Flavor Have Sprinkles?
Resource (Verification Horizons Blog) - Jan 20, 2023 by Chris Spear
UVM is a standard, so that means that every company writes their testbenches the same, universally interchangeable, right? Not exactly. I just got back from teaching in Europe. No matter where the engineers grew up, they all spoke English, each with a different accent. I think that I don’t have an accent, having grown up in Alaska, but my coworkers in Texas and London would disagree. Let’s look at some of the different accents and flavors of UVM.
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Conclusion: Deeper Dive into Non-Trivial Bug Escapes
Resource (Verification Horizons Blog) - Jan 15, 2023 by Harry Foster
Our study results show that the IC/ASIC market has matured its verification processes overtime to address growing complexity, predominately driving by the emergence of SoC-class designs in the mid-2000 timeframe. Today we find the FPGA market is maturing its verification processes.
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Improving Verification Predictability and Efficiency Using Big Data
Resource (Paper (.PDF)) - Jan 10, 2023 by Darron May
This paper will define the typical verification environment and the data that it often leaves uncaptured across the duration of a project. It will show how the process of capture, process, and analyze can be applied to improve predictability and efficiency of the whole verification process.
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Part 12: IC/ASIC Verification Results Trends
Resource (Verification Horizons Blog) - Jan 09, 2023 by Harry Foster
A metric often track to measure efficiency is ASIC project completion compared to the original schedule, as shown in Figure 12-1. Here we found that 66 percent of IC/ASIC projects were behind schedule, while 27% of projects were behind schedule by 27 percent.
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Part 11: ASIC/IC Low Power Trends
Resource (Verification Horizons Blog) - Jan 02, 2023 by Harry Foster
As shown in figure 11-1, we found that 72% of design projects actively manage power. In fact, we found that the larger the design, the greater the concern for power management. Obviously, a wide variety of techniques, ranging from simple clock-gating to complex hypervisor/OS-controlled power management schemes are employed whose requirements require verification.
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Siemens Xcelerator Academy: One Glance - All Trainings
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Guide Your Learning Journey With @oneGlance Maps. Use the maps as visual guides of the recommended flow of learning. Each course entry shows available method of delivery and is linked to course datasheets and sign-up requests.
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Learning Center: QuestaSim Training (Instructor Led)
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Questa Core: HDL Simulation teaches users who are new to using Questa SIM for HDL simulation how to effectively use Questa Core to verify VHDL, Verilog, SystemVerilog, and mixed HDL designs. You will learn how Questa Core supports HDL behavioral simulations, and some basic concepts in the digital design flow. Also, you will receive an introduction on how to invoke the Visualizer debug environment to debug the simulation results from Questa.
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Learning Center: QuestaSim Training (On-Demand)
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Gain mastery of Advanced Questa Simulator’s capabilities to manage your advanced verification environments and debug verification bugs.
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Learning Center: Visualizer Training (On-Demand)
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
The Visualizer course will help you to effectively use Visualizer™ Debug Environment to verify your design and explore your UVM based testbench.
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Learning Center: Visualizer Training (Instructor Led)
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
The Visualizer course will help you to effectively use Visualizer™ Debug Environment to verify your design and explore your UVM based testbench.
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Functional Verification: Self-Paced Library
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
This library contains learning paths that help you master functional verification tools, and the development of test environments using HDL-based methodologies. Learn how to use ModelSim/Questa GUI and command line to verify and debug HDL designs in interactive mode or build batch mode scripts for fast simulations. UVM Framework Verification IP ModelSim / Questa / Visualizer CDC / Lint / HDL Designer Much more 12 month subscription, On-Demand Training
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SystemVerilog for Verification: Self-Paced Course
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Learn about SystemVerilog fundamental and advanced verification constructs. SystemVerilog for Verification / Exam 12 month subscription, On-Demand Training
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SystemVerilog UVM: Self-Paced Course
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Learn how to create a reusable testbench from ground up using SystemVerilog UVM (Universal Verification Methodology) and how to add a UVM Register Model. SystemVerilog UVM / Exam UVM Intermediate / Exam 12 month subscription, On-Demand Training
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Functional Verification: Badging and Certification
Resource (Learning Center) - Jan 01, 2023 by Siemens Learning Center
Test your skills and knowledge, improve productivity and advance your career. Pass any exam and receive a verifiable badge and certificate. To access this library for free, enter promotional code CERTNOW in the shopping cart.
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Part 10: IC/ASIC Language and Library Adoption Trends
Resource (Verification Horizons Blog) - Dec 26, 2022 by Harry Foster
In this blog I plan to discuss various IC/ASIC language and library adoption trends. Figure 10-1 shows the aggregated adoption trends for languages used to create RTL designs across all market segments and all regions of the world. We see continual interest in SystemVerilog for RTL creation.
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Part 8: IC/ASIC Resource Trends
Resource (Verification Horizons Blog) - Dec 18, 2022 by Harry Foster
In this blog, I plan to discuss the growing IC/ASIC project resource trends resulting from growing design complexity. Figure 8-1 shows the percentage of total IC/ASIC project time spent in verification. You can see two extremes in this graph. In general, projects that spend very little time in verification are typically working on designs with a good deal of existing pre-verified design IP, which is integrated to create a new product.
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Part 9: ASIC Verification Technology Adoption Trends
Resource (Verification Horizons Blog) - Dec 18, 2022 by Harry Foster
The ASIC market in the mid-2000 timeframe underwent growing pains to address increased verification complexity, predominately brought on with the adoption of SoC-class designs. This maturing of ASIC projects’ processes is clearly visible when comparing various simulation-based verification technology adoption trends from 2007 through 2022 as shown in Figure 9-1, although the overall dynamic verification technique adoption trends have remained flat for the past few studies.
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Formal Verification of Security Properties
Resource (Recording) - Dec 08, 2022 by Ratish Punnoose - Sandia National Laboratories
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Formal Verification of Security Properties
Resource (Slides (.PDF)) - Dec 08, 2022 by Ratish Punnoose - Sandia National Laboratories
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Harry Foster - Siemens EDA
Resource (Interview) - Dec 08, 2022 by Harry Foster
Interview with Harry Foster of Siemens EDA about the surprising results from the 2022 Wilson Research Study and Osmosis' presentations.
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Holger Busch - Infineon
Resource (Interview) - Dec 08, 2022 by Holger Busch - Infineon
Interview with Holger Busch of Infineon about the origins of formal and how the presentations at Osmosis show how far formal verification has come.
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Katharina Ceesay-Seitz - ETH Zurich
Resource (Interview) - Dec 08, 2022 by Katharina Ceesay-Seitz
Interview with Katharina Ceesay-Seitz of ETH Zurich about the value of attending Osmosis.
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Philippe Luc - Codasip
Resource (Interview) - Dec 08, 2022 by Philippe Luc - Codasip
Interview with Philippe Luc of Codasip about his presentation on How formal lights up your RISC-V verification avenue .
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Saranyu Chattopadhyay - Stanford University
Resource (Interview) - Dec 08, 2022 by Saranyu Chattopadhyay
Interview with Saranyu Chattopadhyay of Stanford University about his presentation on Accelerator quick error detection: Verification of hardware accelerators .