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85 Results

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  Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs

  Article - Jun 15, 2012 by Stephan van Beek, Sudhir Sharma, Sudeepa Prakash - MathWorks

  Chip design and verification engineers often write as many as ten lines of test-bench code for every line of RTL code that is implemented in silicon. They can spend 50% or more of the design cycle on verification tasks. Despite this level of effort, nearly 60% of chips contain functional flaws and require re-spinning. Because HDL simulation is not sufficient to catch system-level errors, chip designers now employ FPGAs to accelerate algorithm creation and prototyping.

• Clock-Domain Crossing

  Topic - by Chris Giles

  Designers increasingly use advanced multi-clock architectures to meet the high-performance and low-power requirements of their chips. An RTL or gate-level simulation of a design that has more than one clock domain does not accurately model the silicon behavior related to the transfer of data between asynchronous clock domains. As a consequence, simulation does not accurately predict silicon functionality, risking show-stopper bug escapes due to metastability. Metastability is a phenomenon that can cause system failures in digital devices when a signal is transferred between circuitry in unrelated or asynchronous clock domains. This topic area focuses on advanced techniques to find clock-domain crossing errors before they escape into silicon.

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  Unit Testing Your Way to a Reliable Testbench

  Article - Jun 06, 2015 by Neil Johnson

  Writing tests, particularly unit tests, can be a tedious chore. More tedious - not to mention frustrating - is debugging testbench code as project schedules tighten and release pressure builds. With quality being a non-negotiable aspect of hardware development, verification is a pay-me-now or pay-me-later activity that cannot be avoided.

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  Breaking Silos: Creating Synergetic Flows for Next-Gen Verification

  Webinar - Oct 08, 2025 by Kirolos Magdy

  In this webinar, through practical demonstrations and real-world examples, you'll see how next-generation verification goes beyond traditional approaches - enabling teams to break down silos, accelerate design cycles, and achieve higher quality results through intelligent automation and collaborative workflows.

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  Formal Etiquette for Code Coverage Closure

  Article - Mar 03, 2021 by Ajeetha Kumari, Arunachalam R and Satheesh Ethiraj - VerifWorks

  Coverage closure is a key step in any IP design verification project. Code coverage is a much-needed metric in most modern-day IP designs. It helps teams to ensure that all RTL code written is indeed exercised and verified prior to tape-out. Without such a guarantee, a semiconductor design house may well be risking millions of dollars in a potential bug-escape to silicon. As the process of code coverage is well automated, it is widely used in the industry.

• Design for Test Verification

  Solution - May 13, 2025 by

  As semiconductor devices become increasingly complex and diverse, spanning automotive, AI/ML, 5G, and heterogeneous 3D-IC designs, Design-for-Test (DFT) verification plays a crucial role in ensuring not only high-test quality but also seamless integration with system-level requirements. While test insertion flows such as scan insertion, BIST/MBIST integration, and boundary scan logic have matured to deliver cost-effective, scalable test solutions, DFT verification remains a bottleneck that demands significant attention.

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  The Six Steps Of RISC-V Processor Verification Including Vector Extensions

  Article - Mar 03, 2021 by Larry Lapides

  The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor verification: The DV Plan, RTL DUT, Testbench, Tests, Reference model, and Siemens EDA Questa SystemVerilog simulation environment.

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  Formal and Assertion-Based Verification of MBIST MCPs

  Article - Jun 06, 2015 by Ajay Daga - FishTail Design Automation

  Built-In Self-Test (BIST) is widely used to test embedded memories. This is necessary because of the large number of embedded memories in a circuit which could be in the thousands or even tens of thousands. It is impractical to provide access to all these memories and apply a high-quality test.

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  Extending SoC Design Verification Methods for RISC-V Processor DV

  Article - Jul 19, 2020 by Larry Lapides

  As SoC developers adopt RISC-V and the design freedoms that an Open ISA (Instruction Set Architecture) offers, DV teams will need to address the new verification challenges of RISC-V based SoCs. The established SoC verifications tasks and methods are well proven, yet depend on the industry wide assumption of ‘known good processor IP’ based on the quality expectations associated with IP providers such as Arm or MIPS Technologies.

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  Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features

  Article - Feb 25, 2013 by Ajeetha Kumari, Srinivasan Venkataramanan - CVC Pvt. Ltd.

  SystemVerilog has become the most widely deployed Verification language over the last several years. Starting with the early Accellera release of 3.1a standard, the first IEEE 1800-2005 standard fueled the widespread adoption in tools and user base. Since 2005 there is no look-back to this "all encompassing" standard that tries to satisfy and do more for RTL Designers and Verification engineers alike.

• Debug

  Topic - by Rich Edelman

  Debugging is a critical aspect of the digital design and integrated circuit design process. It ensures that the designed system or chip functions as intended, identifying and rectifying errors, glitches, and unforeseen issues. Effective debugging saves time and resources, preventing costly mistakes from reaching the final product. It also enhances product reliability, crucial in safety-critical applications, and reduces post-production maintenance. Debugging tools and techniques are essential for engineers to pinpoint and address issues, making the design process more efficient and leading to the creation of high-quality, dependable digital systems and integrated circuits.

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  Improving FPGA Debugging with Assertions

  Article - Sep 10, 2012 by Harry Foster

  Here’s one reason why FPGA design starts dwarf ASIC design starts: choosing flexible, inexpensive and readily available FPGAs is one fairly obvious way to reduce risk when designing complex SoCs for everything from mobile devices and smartphones to automobile electronics.

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  Ten Rules to Successfully Deploy Formal

  Article - Feb 25, 2019 by Dr. Ashish Darbari

  About four years ago I gave a couple of talks on the myths surrounding formal. Although, formal has seen more adoption since then, we have a long way to go before it is recognized as a mainstream technology used throughout design and verification. I still see some of these myths clouding the judgement of end users and their managers.

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  Formal Apps Take the Bias Out of Functional Verification

  Article - Feb 25, 2019 by Bill Au

  When we spend hours, days, or even weeks putting our hearts and minds into creating something, we have a tendency to emphasize its strengths and minimize its weaknesses. This is why verification engineers have a blind spot for their own verification platforms. This blind spot, or bias, often leads to overlooking those areas where bugs may lurk, only to emerge at the worst possible time when errors are most costly and take longer to fix.

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  Sequential Logic Equivalence Checking

  Track - Jul 06, 2021 by Jin Hou

  In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.

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  Veloce Hardware-Assisted Verification – Complete, Unified, and Progressive

  Article - Sep 01, 2021 by Jean-Marie Brunet

  Despite abundant rumors predicting the end of life for Moore’s Law (the axiom stating transistor density doubles every 24 months), semiconductor design sizes continue to grow exponentially with no end in sight. In the process, design sizes push costs off the roof. According to market research International Business Strategies (IBS), the total cost of designing a state-of-the-art system on chip (SoC) at the 5nm process technology node exceeds half a billion dollars.

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  Deploying HLS in a DO-254/ED-80 Workflow

  Article - Sep 01, 2021 by Tammy Reeve - Patmos Engineering Services

  The adoption of tools into safety-critical workflows is often challenging as these new technologies must demonstrate sufficient safeness to use before being deployed in production environments. The demand for High-Level Synthesis capabilities within DO-254 projects is growing and this paper describes the requirements and considerations to successfully use High-Level Synthesis within a DO-254 workflow.

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  Introduction to the Verification Academy

  Session - Feb 25, 2011 by Harry Foster

  This session provides a common framework for all advanced functional verification tracks contained within the Verification Academy.

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  Verify Thy Verifyer

  Article - Mar 01, 2020 by Srinivasan Venkataramanan, Ajeetha Kumari - VerifWorks

  Design Verification is a field that requires a lot of thinking and equally a lot of coding. Tighter time-to-market adds a lot of schedule pressure to the teams coding those testbenches and test cases. The advent of UVM (Universal Verification Methodology) as the standard framework, has helped the industry make good progress in terms of structured testbenches. One of the primary objectives of UVM is to build robust, reusable testbenches.

• FPGA Verification

  Topic - by Moses Satyasekaran

  FPGA (Field-Programmable Gate Array) verification, including methods like simulation and formal verification, is invaluable for ironing out design issues before deploying hardware in the lab. Simulation allows engineers to comprehensively test the FPGA design under various conditions, helping detect and rectify potential bugs and ensuring functionality. By conducting thorough FPGA verification, costly and time-consuming hardware iterations are minimized, significantly reducing the risk of errors and shortening the time-to-lab phase. This approach ultimately leads to more efficient development, lower expenses, and a faster path to achieving operational hardware.

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  Delivering First Silicon Success for Your Next SoC or 3DIC

  Webinar - Apr 25, 2023 by Gordon Allan

  In this session, you will learn about the protocol and memory verification solutions needed for your next silicon verification project whether in Datacenter, Storage, 3DIC, Networking, Automotive or Mil/Aero applications.

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  Equivalence Checking for FPGA

  Webinar - Feb 25, 2022 by Martin Rowe

  In this session, you will learn the need and methodologies to apply Equivalence Checking for FPGAs, plus the advantages and challenges of stepwise netlist verification.

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  Overcoming Today’s Verification, Supply Chain, and Legacy Technology Challenges Associated with FPGA-based Designs

  Webinar - Sep 30, 2022 by Martin Rowe

  In this session you will gain an understanding of the core challenges facing designers of FPGA-based devices. Everything from ensuring the functionality to dealing with FPGA supply chain issues to extending the life of legacy designs powered by old or obsolete FPGAs.

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  System Level Functional Coverage Example

  Chapter - Dec 04, 2013 by Harry Foster

  System level functional verification can take full advantage of the fact that the entire design is a self contained unit that will be used by customers, and thus has some logical use model that the customer will follow. Also, being a system, often it is made up of trusted IP, and the verification focus is aimed more at the block interconnect and any new functionality.

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  QVIP Provides Thoroughness in Verification

  Article - Nov 01, 2015 by Kiran Sharma, Vipin Kumar - Agnisys Technology Pvt. Ltd.

  The present day designs use standard interfaces for the connection and management of functional blocks in System on Chips (SoCs). These interface protocols are so complex that, creating in-house VIPs could take a lot of engineer’s development time. A fully verified interface should include all the complex protocol compliance checking, generation and application of different test case scenarios, etc.