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Find community discussions and expert answers about “rtl quality”

102 Results

Questa Design Solutions as a Sleep Aid

Webinar - Nov 02, 2022 Vinayak Desai

In this session, you will gain an understanding about how Questa Design Solutions can help designers improve the quality of initial deliveries which drives more consistent schedule execution, and fewer late nights for the entire team.
Formal and the Next Normal

Webinar - Oct 19, 2022 Joe Hupcey

In this session, you will learn why formal verification is the key component to succeed in the era of Next Normal (agile and modular adoption), where first pass silicon success is crucial and ensuring quality across you verification cycle is essential.
RTL CDC is No Longer Enough: How Gate-Level CDC is Now Essential to First Pass Success

Article - Jun 28, 2017 Joe Hupcey

Clock-domain crossing (CDC) verification is a critical step in the design verification cycle. However, CDC verification is not only necessary on RTL; at 28nm nodes and below it is also essential on gate-level designs due to the possibility of the introduction of CDC errors during the synthesis phase that can lead to silicon failure. In this article we review the root cause of these challenges and introduce an automated approach to overcome these difficulties.
No RTL Yet? No Problem. UVM Testing a SystemVerilog Fabric Model

Article - Jun 01, 2016 Rich Edelman

SystemVerilog is a powerful language which can be used to build models of RTL in order to facilitate early testbench testing. The early RTL model uses higher level abstractions like SystemVerilog threads, queues, dynamic arrays and associative arrays. Using high level abstractions allows a functional model to be created with little effort. A simple fabric model is created implementing AXI-like READY/VALID channels.
No RTL Yet? No Problem: UVM Testing a SystemVerilog Fabric Model

Paper - Mar 15, 2016 Rich Edelman

This paper describes the implementation of a simple AXI-like skeleton fabric that is used to test the early development of a UVM testbench. It used high-level SystemVerilog features such as threads, dynamic arrays, associative arrays, queues and simple classes to manage the complexity of implementing a real fabric.
Five Steps to Quality CDC Verification

Paper - Mar 13, 2019 Ping Yeung

With the number of clock-domains increasing in today’s complex ASIC designs, the ability to thoroughly verify clock-domain crossings (CDC) has become even more important. As in functional verification, to ensure CDC issues are thoroughly verified, a comprehensive test plan is essential. Based on our experience working with many customers, we developed a five-step planning process for CDC verification.
How Microsemi Uses Questa Formal Connectivity Check to Improve Quality and Productivity

Article - Sep 08, 2017 Mitchell Poplingher

The complexity of our SoCs continues to grow at a furious pace, with a corresponding increase in the integration of more functionality using a massive number of IPs, in addition to the overlay of BIST, multiplexing of I/Os, and other "out of band" circuitry. This complexity makes manual verification of IP integration too risky, time consuming, and error prone.
Fix an FPGA: Ways to Find and Fix FPGA Failures Faster

Webinar - Mar 10, 2022 Buu Huynh

This session will identify how an RTL linting tool embedded within a continuous design checking process during code development and IP block integration can catch bug escapes earlier, while mitigating unforeseen FPGA development and design IP reuse cost.
Exploring the Multifaceted Landscape of Formal Coverage

Webinar - Sep 20, 2023 Nicolae Tusinschi

In this session, you will recognize that formal coverage serves as a barometer for design quality, pinpointing areas that require further scrutiny to achieve robustness.
Four Best Practices for Prototyping MATLAB and Simulink Algorithms on FPGAs

Article - Jun 15, 2012 Stephan van Beek, Sudhir Sharma, Sudeepa Prakash - MathWorks

Chip design and verification engineers often write as many as ten lines of test-bench code for every line of RTL code that is implemented in silicon. They can spend 50% or more of the design cycle on verification tasks. Despite this level of effort, nearly 60% of chips contain functional flaws and require re-spinning. Because HDL simulation is not sufficient to catch system-level errors, chip designers now employ FPGAs to accelerate algorithm creation and prototyping.
Unit Testing Your Way to a Reliable Testbench

Article - Jun 06, 2015 Neil Johnson

Writing tests, particularly unit tests, can be a tedious chore. More tedious - not to mention frustrating - is debugging testbench code as project schedules tighten and release pressure builds. With quality being a non-negotiable aspect of hardware development, verification is a pay-me-now or pay-me-later activity that cannot be avoided.
Breaking Silos: Creating Synergistic Flows for Next-Gen Verification

Webinar - Oct 08, 2025 Kirolos Magdy

In this webinar, through practical demonstrations and real-world examples, you'll see how next-generation verification goes beyond traditional approaches - enabling teams to break down silos, accelerate design cycles, and achieve higher quality results through intelligent automation and collaborative workflows.
Formal Etiquette for Code Coverage Closure

Article - Mar 03, 2021 Ajeetha Kumari, Arunachalam R and Satheesh Ethiraj - VerifWorks

Coverage closure is a key step in any IP design verification project. Code coverage is a much-needed metric in most modern-day IP designs. It helps teams to ensure that all RTL code written is indeed exercised and verified prior to tape-out. Without such a guarantee, a semiconductor design house may well be risking millions of dollars in a potential bug-escape to silicon. As the process of code coverage is well automated, it is widely used in the industry.
Design for Test Verification

Solution - May 13, 2025 Jake Wiltgen

As semiconductor devices become increasingly complex and diverse, spanning automotive, AI/ML, 5G, and heterogeneous 3D-IC designs, Design-for-Test (DFT) verification plays a crucial role in ensuring not only high-test quality but also seamless integration with system-level requirements. While test insertion flows such as scan insertion, BIST/MBIST integration, and boundary scan logic have matured to deliver cost-effective, scalable test solutions, DFT verification remains a bottleneck that demands significant attention.
Future-Proof Your Designs: The Power of Verify Property in Digital Verification

Webinar - Feb 12, 2026 Bobana Brzacki

This webinar reveals cutting-edge tools that empower engineers to identify complex structural issues, connectivity errors, and X-propagation problems early in the design cycle without stimulus generation. Learn how to streamline your verification workflow, accelerate time-to-market, and deliver robust, high-quality designs while significantly reducing costly re-spins and debug cycles.
The Six Steps Of RISC-V Processor Verification Including Vector Extensions

Article - Mar 03, 2021 Larry Lapides

The open standard ISA of RISC-V allows SoC developers to also build or modify a processor core optimized to the application requirements. The SoC verification tasks are adapting to address the significant increases in complexity. This article covers the 6 key components of RISC-V processor verification: The DV Plan, RTL DUT, Testbench, Tests, Reference model, and Siemens EDA Questa SystemVerilog simulation environment.
Formal and Assertion-Based Verification of MBIST MCPs

Article - Jun 06, 2015 Ajay Daga - FishTail Design Automation

Built-In Self-Test (BIST) is widely used to test embedded memories. This is necessary because of the large number of embedded memories in a circuit which could be in the thousands or even tens of thousands. It is impractical to provide access to all these memories and apply a high-quality test.
Unlock Efficiency: Next-Gen Verification with Questa Check Register & Questa Check Connect

Webinar - Feb 26, 2026 Bobana Brzacki

In this webinar you will learn about the automated verification of memory-mapped registers and connections in SOC designs. Questa Check Register and Questa Check Connect eliminate manual errors, accelerate verification processes, and ensure your registers and SOC connections are flawless and reliable. Perfect for teams looking to reduce time-to-market and improve design quality.
Extending SoC Design Verification Methods for RISC-V Processor DV

Article - Jul 19, 2020 Larry Lapides

As SoC developers adopt RISC-V and the design freedoms that an Open ISA (Instruction Set Architecture) offers, DV teams will need to address the new verification challenges of RISC-V based SoCs. The established SoC verifications tasks and methods are well proven, yet depend on the industry wide assumption of ‘known good processor IP’ based on the quality expectations associated with IP providers such as Arm or MIPS Technologies.
Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features

Article - Feb 25, 2013 Ajeetha Kumari, Srinivasan Venkataramanan - CVC Pvt. Ltd.

SystemVerilog has become the most widely deployed Verification language over the last several years. Starting with the early Accellera release of 3.1a standard, the first IEEE 1800-2005 standard fueled the widespread adoption in tools and user base. Since 2005 there is no look-back to this "all encompassing" standard that tries to satisfy and do more for RTL Designers and Verification engineers alike.
Debug

Topic

Debugging is a critical aspect of the digital design and integrated circuit design process. It ensures that the designed system or chip functions as intended, identifying and rectifying errors, glitches, and unforeseen issues. Effective debugging saves time and resources, preventing costly mistakes from reaching the final product. It also enhances product reliability, crucial in safety-critical applications, and reduces post-production maintenance. Debugging tools and techniques are essential for engineers to pinpoint and address issues, making the design process more efficient and leading to the creation of high-quality, dependable digital systems and integrated circuits.
Improving FPGA Debugging with Assertions

Article - Sep 10, 2012 Harry Foster

Here’s one reason why FPGA design starts dwarf ASIC design starts: choosing flexible, inexpensive and readily available FPGAs is one fairly obvious way to reduce risk when designing complex SoCs for everything from mobile devices and smartphones to automobile electronics.
Ten Rules to Successfully Deploy Formal

Article - Feb 25, 2019 Dr. Ashish Darbari

About four years ago I gave a couple of talks on the myths surrounding formal. Although, formal has seen more adoption since then, we have a long way to go before it is recognized as a mainstream technology used throughout design and verification. I still see some of these myths clouding the judgement of end users and their managers.
Formal Apps Take the Bias Out of Functional Verification

Article - Feb 25, 2019 Bill Au

When we spend hours, days, or even weeks putting our hearts and minds into creating something, we have a tendency to emphasize its strengths and minimize its weaknesses. This is why verification engineers have a blind spot for their own verification platforms. This blind spot, or bias, often leads to overlooking those areas where bugs may lurk, only to emerge at the worst possible time when errors are most costly and take longer to fix.
Sequential Logic Equivalence Checking

Track - Jul 06, 2021 Jin Hou

In this track, you will be introduced to the concept of sequential logic equivalence checking and its common applications. You will also learn how to start with Questa® SLEC to verify design optimization, bug fix/ECOs, low power clock gating logic, and safety mechanisms.