Upcoming Debug Webinar

Win the Tick to Trade Race by Root Causing Bugs Faster with QuestaSim

Tuesday, April 16th
8:00 AM US/Pacific

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  1. Session Video

  2. Session Overview

    Ensuring functional correctness on RTL designs continues to pose one of the greatest challenges for today's ASIC, FPGA and SoC design teams. Very few project managers would disagree with this statement. In fact, an often cited 2004 industry study by Collett International Research revealed that 35 percent of the total ASIC and FPGA development effort was spent in verification. In 2008, a Far West Research study (in conjunction with Mentor Graphics) indicated the verification effort has risen to 46 percent of the total ASIC and FPGA development effort.

    Furthermore, these industry studies reveal that debugging is the fastest-growing component of verification, and that it consumes 60 percent of the total verification effort. Unfortunately, with the increase in verification effort, the industry has not experienced a measurable increase in quality of results. For example, a Collett International Research study that focused on design closure indicated that only 29 percent of projects developing ASICs and FPGAs were able to achieve first silicon success. To make matters worse, the industry is witnessing increasing pressure to shorten the overall ASIC, FPGA and SoC development cycle. Clearly, new design and verification techniques, combined with a focus on evolving an organization's functional verification process capabilities are required.

    Functional verification flows that consist entirely of directed test and code coverage approaches (circa 1990 best practices) struggle to keep pace with today's verification challenges. In fact, there have been many helpful verification technologies that have emerged in the past 15 years (such as constrained-random, coverage-driven simulation; formal property checking; and assertion-based verification) that have demonstrated value by increasing productivity and achieving higher quality, as indicated both by those achieving first silicon success in the Collett and Far West studies.

    This session provides a common framework for all advanced functional verification modules contained within the Verification Academy. A simple Evolving Capabilities model is presented, which can be used as a tool for assessing an organization's functional verification process capabilities.