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209 Results

  • Validation of Complex Safety Architectures

    This session explains the methodology and flow of how to perform an accurate safety analysis, followed by fault simulation on the SoC or IP with a combination of hardware and software safety mechanisms.

  • Acceleration Without Compromise: How to Finish Faster with Hierarchical CDC+RDC Methodologies

    In this session, you will learn how to properly deploy hierarchical methodologies in CDC and RDC verification such that neither accuracy nor the performance expected from a hierarchical flow is compromised.

  • CDC Philosophy: The Existential Questions of Constraints, Waivers, and Truth

    In this session we will increase your confidence that the CDC results you see are truly reflective of the quality of your design. Using automated assertion-based verification flows and other verification techniques, the designer can know that the constraints and waivers applied are applied correctly.

  • Improving Initial RTL Quality

    This session will help you lower risks and improve team agility and development consistency by optimizing verification. Using designer-driven verification flows, designers get intent-focused insight to find issues when they are cheapest and easiest to fix.

  • IP Security: Keys to Early Identification of Security Vulnerabilities

    In this session we will demonstrate early security verification on a small module of intellectual property (IP) intended for integration into an IC. Using Methodics IPLM by Perforce’s key technology for IP management and OneSpin 360™ formal verification tools, our technical experts will jointly perform the process recently released for public comment in the Accellera Secure Annotation for Electronic Design Integration (SA-EDI) Standard.

  • Reset-Domain Crossing Overview & Questa RDC Methodology

    In this session, you will learn more about Reset-Domain Crossing problems and methods to address it. Then you will be introduced to the Questa RDC solution, how it catches true RDC issues and what is our proposed methodology of RDC flow to filter noise and have better QoR.

  • Should I Kill My Formal Run? Part 1: Formal Run is In-Progress

    In this session we will show you the information you can use to decide whether to continue or stop the formal job such as how to monitor the formal engines’ “health” in real time and why a given property analysis might be getting stuck.

  • Exploration into Safety Analysis Techniques That Optimize the Safety Workflow

    In this session, you will gain an understanding of how Siemens EDA provides a methodology that results in achieving a single iteration around costly fault injection, resulting in a more predictable project schedule and an accelerated time-to-certification.

  • Managing Requirements in a Functional Safety Environment

    In this session, you will learn that Requirements Management in a "Functional Safety" environment can be very challenging. With Polarion ALM you have a comprehensive solution at hand that fully supports you in successfully managing not only the pure requirements themselves but also all related processes.

  • Using Formal Verification in Daily Work

    In this session, we will describe some typical formal applications and how the formal results can be integrated with other verification results.

  • Digital Functional Verification for Safety-Critical Automotive Applications

    In this session, you will be shown a coverage driven verification flow based on the Questa platform. You will also learn how a web-based platform helps to finalize the project successfully even in teams spread over multiple locations.

  • CDC Verification: Beyond Structural Analysis

    In this session, we will cover the overall CDC methodology and cover CDC protocols and reconvergence in more details and show what could happen if these steps are skipped.

  • Mitigating the Effects of Random Hardware Faults

    Random faults cannot be prevented so the goal there is to sufficiently tolerate them. With random faults you are really just trying to make sure that the product will fail safely when inevitably one of these random hardware faults occurs. In this session we will outline approaches on how to tackle systematic as well as random faults.

  • AMS Functional Verification for Safety-Critical Automotive Applications

    In this session, you will learn how Siemens EDA Symphony platform addresses today's nanometer mixed signal verification challenges for safety-critical automotive applications.

  • A Path to Develop Safe ICs - Part 2

    In this session you will learn that Siemens EDA has developed a platform that allows early collaboration between OEMs and their suppliers. It provides a clear definition of requirements and allows hardware and software functionality to be tested in a virtual environment long before silicon is available.

  • A Path to Develop Safe ICs - Part 1

    In this session, you will learn that Siemens EDA helps customers adapt to the required development flows, develop safety collateral for their designs, and mitigate the risk of product failure in safety critical applications.

  • Extending the Role of Test and In-System Test to Meet Automotive Safety and Security Requirements

    In this session, we will show how Design For Test is expanding from its traditional role into one that includes the management of the entire silicon lifecycle, to become Silicon Lifecycle Solutions. Ensuring that ICs work safely as expected and are secure throughout their operational life.

  • Hardware-Accelerated & Software-Driven Verification

    In this session we will talk about ease of adopting Emulation and various ways of using the powerful Apps that bring in software to improve accuracy of verification process.

  • Automotive SOTIF Compliance for Arm with PAVE360

    In this session, we will explain Safety Of The Intended Function (SOTIF) and demonstrate techniques to prove systems.

  • Are Random Hardware Faults Common?

    In this session, you will be given an introduction of solutions to analysis failure modes resulting from random hardware faults. These can guide the user to unsafe areas of the design where safety mechanisms need to be inserted.

  • Traceability for Automotive Standards Compliance

    In this session, you will learn how the combination of Siemens Polarion ALM Requirements Management and Questa Verification Management solve the lifecycle management and traceability requirements for Automotive projects.

  • The Future of Automotive and its Impact on Safety

    This session will provide a perspective on the impact to companies developing automotive ICs and serves as the introduction to the multi-part automotive safety webinar series covering many aspects of an automotive safety lifecycle.

  • Part II: Verification of PCIe® IP

    In the second of two joint webinars, PLDA and Siemens EDA present what you need to know about Gen 6 to build and verify your design using the updated protocol. In our first webinar, we focused on the differences between the older and new specifications. In this second session, we return to design considerations, then take a deep dive into how to verify your design.

  • Leveraging Advancements in UPF 3.1 for Effective Design and Verification

    In this session, you will learn about some of the new syntax and semantic capabilities and clarifications introduced in IEEE1801-2018 (UPF 3.1), typical use cases that prompted the addition or change and highlight any semantic differences with previous versions of the standard where applicable.

  • Part I: Introduction to PCIe® Gen 6

    In this first of two joint webinars, PLDA and Siemens EDA join to introduce you to PCIe® 6.0, including architecture differences from prior generations, performance improvements, and how PCIe 6.0 compares from both a designer and verification perspective.