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35 Results

• Introduction to the UVM

  Track - Aug 04, 2014 by Ray Salemi

  This track will guide you from rudimentary SystemVerilog through a complete UVM testbench. Each session is designed to give you the minimal amount of knowledge necessary to make it to the next level. Once you have worked through all these sessions, you will have experience with all the major components of the UVM as well as their concepts. You are then ready to learn more advanced techniques.

• Power Aware Verification

  Track - Apr 05, 2013 by Erich Marschner

  This track introduces the IEEE Std 1801 Unified Power Format (UPF) for specification of active power management architectures and covers the use of UPF in simulation-based power aware verification.

• VHDL-2008 Why It Matters

  Track - Jan 17, 2013 by Jim Lewis

  VHDL-2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed and floating point math packages.

• FPGA Verification Capabilities

  Track - Aug 30, 2012 by Ray Salemi

  This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.

• Metrics in SoC Verification

  Track - Jun 01, 2012 by Andreas Meyer

  In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.

• Testbench Co-Emulation: SystemC & TLM-2.0

  Track - Oct 27, 2011 by John Stickley

  This track advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements.

• CDC Verification

  Track - Feb 25, 2011 by Harry Foster

  This track introduces a set of steps for advancing an organization’s clock-domain crossing (CDC) verification skills, infrastructure, and metrics.

• SystemVerilog Testbench Acceleration

  Track - Feb 25, 2011 by Hans Van Der Schoot

  This track will give you the confidence required to start the process of investigating and creating a single testbench environment for both simulation and hardware-assisted acceleration.

• Verification Planning and Management

  Track - Feb 22, 2011 by Peet James

  This track will define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project.

• Assertion-Based Verification

  Track - Feb 10, 2010 by Harry Foster

  This track introduces a set of steps for advancing an organization’s assertion-based-verification (ABV) skills, infrastructure, and metrics.