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Formal-Based Technology
Track - Jun 05, 2015 by Harry Foster
This track introduces basic concepts and terminology that should be useful by any engineer wishing to mature their formal-based technology skills. In addition, this track presents use models and guidelines for integrating formal property checking into a project’s verification flow.
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Formal Assertion-Based Verification
Track - Jun 05, 2015 by Mark Eslinger
In this track, you will learn how to get started with direct property checking including: test planning for formal, SVA coding tricks that get the most out of the formal analysis engines.
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Introduction to the UVM
Track - Aug 04, 2014 by Ray Salemi
The Introduction to the UVM (Universal Verification Methodology) course consists of twelve sessions that will guide you from rudimentary SystemVerilog through a complete UVM testbench.
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Power Aware Verification
Track - Apr 05, 2013 by Erich Marschner
This track introduces the IEEE Std 1801 Unified Power Format (UPF) for specification of active power management architectures and covers the use of UPF in simulation-based power aware verification.
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VHDL 2008: Why It Matters
Track - Jan 17, 2013 by Jim Lewis
VHDL 2008 matters because it facilitates advanced verification, adds reusable data structures, simplifies RTL coding and adds fixed- and floating-point math packages. VHDL 2008 is the largest change to VHDL since 1993; this track is designed to explain the value of the new VHDL 2008 improvements for both Design and Verification Engineers. It is time to start using the new language features to simplify your RTL coding and facilitate the creation of advanced verification environments.
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FPGA Verification Capabilities
Track - Aug 30, 2012 by Ray Salemi
This track introduces techniques for addressing complexity by evolving your organization’s FPGA verification process capabilities.
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Metrics in SoC Verification
Track - Jun 01, 2012 by Andreas Meyer
In this track, we take a broader view of metrics—beyond traditional coverage measurements—that identify a range of metrics across multiple aspects of today’s SoC functional verification process. We then discuss other important considerations when integrating metrics into a project flow, such as metric categorization, run-time control, data management, and reporting and analysis.
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Testbench Co-Emulation: SystemC & TLM-2.0
Track - Oct 27, 2011 by John Stickley
This track advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements.
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CDC Verification
Track - Feb 25, 2011 by Harry Foster
This track introduces a set of steps for advancing an organization’s clock-domain crossing (CDC) verification skills, infrastructure, and metrics.
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SystemVerilog Testbench Acceleration
Track - Feb 25, 2011 by Dr. Hans van der Schoot
This track advocates that functional verification through modern testbenches paired with co-emulation enables further verification productivity improvements in terms of raw performance. This track is primarily aimed at existing SystemVerilog H/W engineers or managers who recognize they have a functional verification throughput problem but have little or no experience with using emulation as a means for accelerating SystemVerilog testbench environments.
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Verification Planning and Management
Track - Feb 22, 2011 by Peet James
In this track, you will learn how to architect an overall verification approach, and then to document that approach in a family of useful, easily extracted, maintainable verification documents that will strategically guide the overall verification effort so that the most amount of verification is accomplished in the allotted time. We will also define terms, logically divide up the verification effort, and lay the foundation for actual verification planning and management on a real project.
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Assertion-Based Verification
Track - Feb 10, 2010 by Harry Foster
This track introduces a set of steps for advancing an organization’s assertion-based-verification (ABV) skills, infrastructure, and metrics.