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Display uvm_info including ps values
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7
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100
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November 23, 2025
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Is there any way to merge two types of code coverage and show the total between them
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2
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130
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November 21, 2025
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SVA sequence re-triggers on multiple $fell events – rise_t not updating
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1
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67
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November 19, 2025
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Continuous assignment between two inout
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3
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60
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November 19, 2025
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Redefine a SV interface port direction in a modport
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2
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91
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November 19, 2025
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What are the best Python-HDL/HLS/HVL Bridges/Interfaces/Communications Modules?
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0
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143
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November 17, 2025
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Wait_for_state() in a static module doesn't work as expected
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10
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201
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November 16, 2025
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UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses
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2
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97
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November 13, 2025
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Individual field access causes extra reads/writes?
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5
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62
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November 12, 2025
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Resume simulation when any 2 threads out of 3 get completed within fork-join_any
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9
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4321
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November 12, 2025
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Verifying synchronours fifo
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3
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144
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November 11, 2025
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Question regarding followed by operator in SVA (#-# and #=#
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0
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73
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November 11, 2025
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System verilog constraint help
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2
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152
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November 11, 2025
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UVM RAL: How to execute register access without updating mirrored value?
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1
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111
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November 8, 2025
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VHDL Code Coverage - Generate Statements
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2
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83
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November 6, 2025
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Code debug help
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2
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110
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November 5, 2025
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Chained Implications in SVA
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0
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85
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November 3, 2025
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Why only ##1 (single delay operator) used in the case of multiple clock sequences?
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2
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695
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November 3, 2025
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Vertical re-use (from block to sub-system/chip level)
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5
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3413
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November 2, 2025
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Migrating from IP to sub-system level
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2
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116
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November 2, 2025
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restricting sequence as long as one variable is asserted
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4
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99
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November 2, 2025
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Default value of enumarated varaible is first value of enum
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4
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92
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November 1, 2025
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difference b/w nexttime and ##1
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1
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76
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October 31, 2025
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Why ref bit and int doesnt Work in sampling but int andref bit Does
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0
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74
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October 31, 2025
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Paper: Understanding SVA Degeneracy
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9
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641
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October 29, 2025
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In my design, I have an assign statement like assign var = (a == b) ? 1 : 0;. During simulation, var takes both values 1 and 0 as expected, but in Questa code coverage, this statement is still shown as not covered. Why is this happening?
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2
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64
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October 29, 2025
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SVA with multiple Implication operators
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0
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72
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October 29, 2025
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Why uvm_object_registry is called as lightweight proxy?
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1
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85
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October 28, 2025
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Function inside constraint
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1
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120
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October 28, 2025
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UVM Class Hierarchy ? can any one help me by giving me the full uvm base class hierarchy structure
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5
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177
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October 27, 2025
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