Continuous assignment between two inout

SystemVerilog
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1

Dear forum,

I want to use a continuous assignment between two inout (lets say ‘a’ and ‘b’).
From circuit point of view what is the is correct syntax ? i.e :

  • is correct if I use only one assignment ? assign a= b OR assign b=a

  • I need to use two assignments ? assign a= b; assign b=a

  • a tri state ?

  • …

    Thanks

2

There are several options:

  1. Use a common wire to connect the two ports.
  2. Use a ‘let’ statement to redefine one wire with another name.
  3. Use a ‘tran’ primitive.
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3

Thanks @cgales !

What if I use only a simple (and arbitrary lhs/rhs) assignment : assign a = b;

From circuit point of view it makes sense ?

in other words :

assign a = b; and assign b = a; are equivalent ?

4

An assign statement is meant to model combinatorial logic and is one direction. The statement

assign a = b;

will result in the behavior that anytime b changes, the value of a will be updated. Any updates to a will not change b.

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