Why only ##1 (single delay operator) used in the case of multiple clock sequences?

SystemVerilog
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1

Hi,

My question is related to assertions.

Why ##1 is used when it comes to multiple clock sequences.
What happens if ##2 is used.

Please help me understand.
Thanks in advance.

2

In reply to sk7799:

Multiclocking is allowed after the ##0 or the |-> (same timing effect) and the ##1 or the |=> (same timing effect) See
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3

This is quite curious; and caught me a bit by surprise: according to IEEE 1800-2023 F.3.4.2.2

[let m> 1] (R1 ##m R2) \equiv ( R1 ##1 1[*m – 1] ##1 R2 )

As long as R1 and R2 are clocked sequences, R1 Clock should extend up to where R2’s starts, hence if we can define the meaning of ##1 [@(c_{R2})] R2 we should be able to have an applicable semantics for R1 ##n R2.

This is, though, in contrast with the content of clause 6.13.1, that allows only ##0 and ##1 as legal concatenations between clocked sequences, for a reason I do not follow: it seems to me that from F.3.4.2.2 the clocking expression of R1 should span as far as the R2 clocking expression gets into action, giving the 1##[*m-1] to be clocked by c_{R1}.

It’s obviously clear that, as long as the standard restrains the multiclock concatenation to just ##0 and ##1 cases, we cannot have ##n, with n>1, but I think this is NOT a needed restriction.