UVM RAL: How to execute register access without updating mirrored value?

UVM
1

I am using UVM 1.2c with auto-predict.

Based on some dynamic configuration, some registers can be accessed or not.

For testbench, this means that I need to execute the register access (write with random value or read) but the access should fail (mirrored value not be updated in case of write and return 0 in case of read).

How can I achieve this?

I tried to upodate the adapter and set rw.status = UVM_NOT_OK but it doesn’t have any effect over mirrored value (it gets updated even if I don’t want to).

I tried to add a callback, but:

  • pre_write modifies the value to be written (i don’t want to)
  • write cannot be updated
  • post_write occurs after the predict happens

Any sugestions?

2

Just an idea :: What if one were to disable the auto_predict mechanism during specific access ?