Topics tagged uvm-register-model

Topic	Replies	Views	Activity
UVM 1800.2 (2020.3.1) - Individual accesses have wrong addresses UVM SystemVerilog , UVM , uvm-register-model	2	98	November 13, 2025
Individual field access causes extra reads/writes? UVM SystemVerilog , UVM , uvm-register-model	5	62	November 12, 2025
Poll for a status register until we see desired read value SystemVerilog uvm-register-model , poll-read	2	124	July 29, 2025
Requirement of both local_map & map UVM RAL , uvm-register-model	2	127	October 30, 2024
UVMF register model access from interface responder sequence UVM UVM , uvm-register-model , UVMF , responder	1	464	November 10, 2023
Invalid Register access UVM UVM , RAL , uvm-register-model , -UVM-warnings-disable	4	965	February 6, 2023
Hdl path to memory instance UVM UVM , UVM-MEMORY-MODELING , uvm-register-model , uvm-backdoor-register-model , Backdoor_access-HDL-access-methods	1	1211	November 17, 2022
UVM reg sublocks UVM UVM , uvm-register-model , uvm-reg-model	1	826	July 26, 2022
UVM register model conflict UVM UVM , Advanced-UVM-Register , register-adapter , uvm-register-model	4	2697	April 27, 2022
Unable to compile a register model using registers of size 2048 bits UVM UVM , questasim , UVM-Questa , uvm-register-model	12	2480	March 16, 2022
Reset WO register fields UVM UVM , uvm-register-model	1	576	October 24, 2021
Passing the register model handle to the sequence UVM UVM , uvm-register-model	2	1064	September 5, 2021
How to do register model write read test(frontdoor, backdoor)? UVM UVM , UVM_reg_field , ral-backdoor , uvm-register-model , Register-Access	3	1165	January 19, 2021
Poke and peek method(Register model) UVM UVM , uvm-register-model	4	5626	June 2, 2020
Getting around UVM/REG/DUPLROOT UVM UVM , Advanced-UVM-Register , uvm-register-model	4	3482	March 25, 2020
Register model access from C UVM UVM , uvm-register-model , SV_DPI-C-based-testing-SV-UVM	1	1554	March 18, 2020
Register Abstraction Layer UVM UVM , uvm-register-model	0	1384	June 20, 2019
Multi layered virtual sequences and grabbing a sequencer UVM UVM , sequencer , virtual-sequence , uvm-register-model , sequence-hierarchy , grabing-sequencer	1	1335	January 10, 2019
Vlog not accepting +define for UVM_REG_ADDR_WIDTH/UVM_REG_DATA_WIDTH UVM UVM , uvm-register-model	6	2866	March 27, 2018
Why predict function of register model should update the .value variable that is used for randomization? UVM UVM , aliased-registers , Methodology , Advanced-UVM-Register , uvm-register-model	0	1283	October 13, 2017
Register model initial values UVM UVM , uvm-register-model	6	3226	March 2, 2017
Paging a uvm block in regmodel UVM UVM , uvm-register-model , UVM-register-mapping-pages , paging	0	1735	January 3, 2017
Register adapter using sequence layering UVM UVM , Sequence-Layering , register-adapter , uvm-register-model	1	1370	May 18, 2016