How to do register model write read test(frontdoor, backdoor)?

UVM
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1

Hi,I’m doing register model test right now.
I want to write from frontdoor, read from backdoor.
then, write from backdoor, read from frontdoor.

But because the dut didn’t list every reg, but reg field in every register,
so I can’t use the build in sequence uvm_reg_access_seq.

my solution is write 1 to the reg from frontdoor, then read every reg field using absolute path.
like this:

      rgm.Control_Register_0.write(status,1,UVM_FRONTDOOR);
      rgm.Control_Register_0.CHEN0.read(status,value);
      rgm.Control_Register_0.CHEN1.read(status,value);
      rgm.Control_Register_0.PDMEN.read(status,value);

my definition of absolute path:

`define PDMEN_PATH tb_top.my_pdm.pdm_reg.pdmen_reg

but vcs will give warning below:

Individual field access not available for field . Accessing complete register instead.

How to solve this problem?

2

In reply to Xiang.L:

Two things:
(1) you do not show how the access policy of the reg fileds is.
(2) your read and write command is the 3rd argument (parent) missing.

3

In reply to chr_sue:
the access policy is RW
I tried not to use the read function, but read directly from the absolute path of the reg field. It worked.
anyway, thank you!

4

In reply to Xiang.L:

But then you do not need the RAL.