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Register Active Monitoring in UVM
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4
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1515
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March 4, 2025
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UVM register model conflict
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4
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2677
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April 27, 2022
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Getting around UVM/REG/DUPLROOT
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4
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3468
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March 25, 2020
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Need bus2reg access in register sequence
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0
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724
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August 26, 2019
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How to create regAdapter for pipelined protocol like AHB
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2
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1914
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January 11, 2019
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UVM_RAL Frontdoor write & write_reg
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9
|
4054
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April 28, 2018
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RAL adapter and predictor
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5
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4813
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April 17, 2018
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Register adaptor completing sequence problems
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10
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3490
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January 30, 2018
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Why predict function of register model should update the .value variable that is used for randomization?
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0
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1277
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October 13, 2017
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Register Addressing RAL
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0
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1309
|
September 8, 2017
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Broadcast register read/write with RAL
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1
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2087
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September 7, 2017
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How to do uvm built in bit-bash sequence /read-write on Indirect addressed registers?
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0
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1800
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May 14, 2017
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How to verify scanchains using UVM?
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1
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1382
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January 26, 2017
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How to make some registers of DUT as not Accessible to the customer
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3
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1820
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November 14, 2016
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Looking for an exercise materials to challenge myself in SystemVerilog and UVM preferably with solution
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2
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3865
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August 31, 2016
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Need uvm_spi_bl_reg_tb register model block diagram?
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0
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1084
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August 25, 2016
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Modeling registers of a chip
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9
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2921
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June 9, 2016
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Multi level defines required
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7
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2152
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May 25, 2016
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UVM 1.1d reg write/read ordering
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1
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1258
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May 17, 2016
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Possible Error in Advanced UVM Session 8 Register Example
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0
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1098
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March 17, 2016
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