UVM 1.1d reg write/read ordering


I’ve been using the uvm_reg write/read operations, for 64-bit registers with a 32-bit interface (APB for example), I see that the write(), and read() tasks are able to send two bus accesses first lower-part, the upper-part. Is it possible to reorder this in a “random” way, let’s say for some registers do first the upper-part first then the lower-part? Or for example writing only one half of the register, and then another register?

Any example is really appreciated.


This is possible out of the box in UVM 1.2. There’s a uvm_reg_transaction_order_policy that you can extend and use in conjunction with uvm_reg_map. I didn’t see any examples in the distribution.

If you’re using earlier versions of UVM, you can use a frontdoor sequence. This is described in the user guide.