hello everyone,
I am trying register model front door access. when i use write & write_reg methods to write in to registers, simulation gets hangs. i am not able find the problem. Here is the whole code i have written
//sequence
class reg_seq extends uvm_sequence;
//instance of reg block
apb_reg_block apb_rb;
function new(string name = "");
super.new(name);
enfunction
apb_rb.ld_reg.set(32'hb);
data= apb_rb.ld_reg.get();
apb_rb.ld_reg.write(status,data,.parent(this));
endclass
/////////////==========virtual sequence class=========///////////////
class vir_reg_sequence extends virtual_sequence;
`uvm_object_utils(vir_reg_sequence)
//*********************constructor***********************
function new (string name="vir_reg_sequence");
super.new(name);
endfunction:new
//*********************body method***********************
task body();
super.body();
reg_seq=reg_sequence::type_id::create("reg_sequence");
wreg_seq=wdog_read_default_values::type_id::create("wdog_read_default_values");
fork
`uvm_info("VIRTUAL SEQUENCE T.C. 10","///////In Body of Virtual Sequence T.C. 5 ////////",UVM_MEDIUM)
reg_seq.start(vir_seqrh.master_seqrh[0]);
wreg_seq.start(vir_seqrh.slave_seqrh[0]);
join
endtask
endclass
////////================adapter class=================////////
class reg_adapter extends uvm_reg_adapter;
`uvm_object_utils(reg_adapter)
function new(string name = "reg_adapter");
super.new(name);
supports_byte_enable =0;
provides_responses = 1;
endfunction
virtual function uvm_sequence_item reg2bus(const ref uvm_reg_bus_op rw);
master_trans trans = master_trans::type_id::create("trans");
if(rw.kind == UVM_WRITE) begin
trans.pwrite = (rw.kind == UVM_WRITE) ? UVM_WRITE: UVM_READ;
trans.paddr = rw.addr;
trans.pwdata = rw.data;
trans.penable=1'b1;
trans.presetn=1'b1;
trans.psel=1'b1;
`uvm_info("REG2BUS_W",$sformatf("printing from the adapter reg2bus write access \n %s",trans.sprint()),UVM_LOW)
end
else if(rw.kind == UVM_READ) begin
trans.pwrite=1'b0;
trans.paddr=rw.addr;
`uvm_info("REG2BUS_R",$sformatf("printing from the adapter reg2bus read access \n %s",trans.sprint()),UVM_LOW)
end
return trans;
endfunction
virtual function void bus2reg(uvm_sequence_item bus_item,ref uvm_reg_bus_op rw);
master_trans trans;
if(!$cast(trans,bus_item)) begin
`uvm_fatal("APB_ADAPTER", "cast failed in the adapter" );
return;
end
rw.kind = trans.pwrite ? UVM_WRITE :UVM_READ;
if(rw.kind == UVM_WRITE) begin
rw.addr = trans.paddr;
rw.data = trans.pwdata;
`uvm_info("BUS2REG_W",$sformatf("printing from the adapter bus2reg write access \n %s",trans.sprint()),UVM_LOW)
end
else if(rw.kind == UVM_READ) begin
rw.addr = trans.paddr;
rw.data = trans.prdata;
`uvm_info("BUS2REG_W",$sformatf("printing from the adapter bus2reg read access \n %s",trans.sprint()),UVM_LOW)
end
rw.status = UVM_IS_OK;
endfunction
endclass
///////////=============register class==============///////////
class load_register extends uvm_reg;
`uvm_object_utils(load_register)
rand uvm_reg_field ld_reg;
function new(string name="load_register");
super.new(name,32,UVM_NO_COVERAGE);
endfunction
virtual function void build();
ld_reg = uvm_reg_field::type_id::create("ld_reg");
ld_reg.configure(this,32,0,"RW",0,'hFFFFFFFF,1,1,0);
endfunction
endclass
/////////////////////============register block===========////////////////
class apb_reg_block extends uvm_reg_block;
`uvm_object_utils(apb_reg_block)
rand load_register ld_reg;
uvm_reg_map apb_map;
function new(string name = "apb_reg_block");
super.new(name,UVM_NO_COVERAGE);
endfunction
virtual function void build();
ld_reg =load_register::type_id::create("load_register");
ld_reg.configure(this,null,"");
ld_reg.build();
ld_reg.add_hdl_path_slice("load_register",0,32);
apb_map = create_map("apb_map",'h0,4,UVM_LITTLE_ENDIAN);
default_map = apb_map;
apb_map.add_reg(ld_reg,'h0000,"RW");
add_hdl_path("top.DUT.u_apb_watchdog_frc","RTL");
lock_model();
endfunction
endclass
///////////==========environment==========//////
class tb extends uvm_env;
`uvm_component_utils(tb)
//adapter instance
reg_adapter adapter_h;
//predictor
uvm_reg_predictor#(master_trans) predictor_h;
//*******************************Build_phase*******************************
function void env ::build_phase(uvm_phase phase);
super.build_phase(phase);
//predictor creation
predictor_h = uvm_reg_predictor#(master_trans)::type_id::create("predictor_h",this);
//Adapter creation
adapter_h = reg_adapter::type_id::create("adapter_h",this);
endfunction:build_phase
if(env_cfg.apb_rb.get_parent== null) begin
env_cfg.apb_rb.apb_map.set_sequencer(.sequencer(master_top.agent_h[0].seqr_h), .adapter(adapter_h));
end
predictor_h.map = env_cfg.apb_rb.apb_map;
predictor_h.adapter = adapter_h;
env_cfg.apb_rb.apb_map.set_auto_predict(0);
master_top.agent_h[0].monitor_h.monport.connect(predictor_h.bus_in);
endclass
///////////==============test============////////
class test_reg_seq extends test;
`uvm_component_utils(test_reg_seq )
//Declaring handle of virtual default sequence
vir_reg_sequence vir_reg_seq;
//*********************************Run_phase***************************
task test_reg_seq::run_phase(uvm_phase phase);
phase.raise_objection(this);
super.run_phase(phase);
//Creating handle of virtual sequence
vir_reg_seq=vir_reg_sequence::type_id::create("rg_seq_h");
//rg_seq_h.model=reg_block_h;
vir_reg_seq.start(tb_h.vir_seqr_tb);
phase.drop_objection(this);
endtask
endclass