UVM_RAL Frontdoor write & write_reg

In reply to chr_sue:

Thanks a lot it worked for me.

I assigned this handle in reg_seq and it worked fine.

apb_rb.ld_reg.read(status,value,.parent(this));

But when i’m use this read method simulation gets hang only for read not for write operation and I found that the problem is in my monitor(forever loop). and I didn’t understood one thing is that it is not coming out from the loop, is there any problem in the predictor monitor connection. if you could help me from this it will be really helpful, Here is my monitor logic


class master_monitor extends uvm_monitor;
`uvm_component_utils(master_monitor)
//transaction handle
master_trans mon_txn

uvm_analysis_port #(master_trans) monport;
//constructor
//build_phase 
mon_txn = master_trans::type_id::create("mon_txn");

//run_phase

task master_monitor::run_phase(uvm_phase phase);
forever begin 
if(vif.apb_monitor_cb.penable) begin 
@(vif.apb_monitor_cb);
mon_txn.paddr= vif.apb_monitor_cb.paddr;
mon_txn.pwdata= vif.apb_monitor_cb.pwdata;
end
monport.write(mon_txn);
endtask
endclass