How to verify scanchains using UVM?

UVM
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I have this specific design which has lot of scanchains in RTL. I have to verify scanchains by scanning in and scanning out a particular pattern.There are many such scan chains. Scan chains are of variable length depending on test.

Scanning in is one single step process and it is done through the task when all the data is received.
Protocol part is done in the task but complete data should be ready before we call the task. How should be send this data to driver ? I can send data to driver Bit by bit/group of bits but then driver should wait till all the bits are received while also storing the received bits for processing. Sending data vector varies in length based on the type of test and there are many such scanchains.

Are there any examples of verifying scanchains in UVM ? I explored Register modeling and it would not see to fit the requirements. I am newbie in UVM and any suggestions are highly appreciated

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In reply to Varunshivashankar:

One key attribute about being a good verification engineer is using the right tool for the job at hand. I’m sure you could write a UVM testbench to verify scanchains, but there are existing tools that are designed specifically for scanchain pattern generation and testing. I would highly recommend looking at those tools instead of trying to use UVM.