Register Addressing RAL

I already have a working UVM RegModel built for an IP (class IP_regmodel)
Now I have to instantiate this IP two times in my Testbench.
How can I extend this RegModel now? Because the register addresses for both the IPs are the same.
Any suggestions would be of great help!

I tried it the following way and it doesn’t not (I used the MSB to differentiate between the base address of both IPs and Offset addresses are the same)

class IPs_regmodel extends uvm_reg_block;
rand IP_regmodel model1;
rand IP_regmodel model2;

constraint user_defined;

function new(string name = “IPs_regmodel”);
super.new(name);
endfunction: new

function void build();
this.default_map = create_map(“”, 0, 4, UVM_LITTLE_ENDIAN, 0);

this.model1 = IP_regmodel::type_id::create("model1",,get_full_name());
this.model1.configure(this, "");
this.model1.build();
this.default_map.add_submap(this.model1.default_map, `UVM_REG_ADDR_WIDTH'h0);

this.model2 = IP_regmodel::type_id::create("model2",,get_full_name());
this.model2.configure(this, "");
this.model2.build();
this.default_map.add_submap(this.model2.default_map, `UVM_REG_ADDR_WIDTH'h1000_0000); 

endfunction : build

`uvm_object_utils(IPs_regmodel)
endclass : IPs_regmodel