Function inside constraint

SystemVerilog
1

Write constraint for the below requirements :
a.​ The queue size will be 15. Randomize a queue such that it exactly has four 7 in it.
b.​ No 7’s should be at the consecutive next to each other

class queue_7;rand bit [3:0] queue[$];

constraint queue_size_c {queue.size() == 15;}

constraint queue_element_c {foreach(queue[i]){if(i >0 && queue[i-1] == 7)queue[i] !=7;}queue.sum with(int’(item ==7)) == 4;}

function void post_randomize();$display(“queue %p”,queue);endfunction

endclass

instead of using array in built function i was thinking to use function

function int unsigned count(bit[3:0] array[$]);

 foreach(array[i])
  if(array[i] == 7)
     count++;

endfunction

constraint queue_element_c {foreach(queue[i]) {if(i >0 && queue[i-1] == 7)
queue[i] !=7;}
count(queue) == 4;}

solver is failing to solve this but in built function it is resolving. Imn trying to understand behind the scene

@dave_59

2

The “Functions in constraints” section of the LRM outlines the requirements and behavior for functions used in constraints. Importantly, it states that the functions are called before randomization, and the return value is used as a “state variable” for randomization.

So why does $countones work the way it does? I don’t know about other simulators, but the one I use documents that $countones specifically has been augmented to work as a bidirectional constraint instead of the usual function call behavior.