Redefine a SV interface port direction in a modport

SystemVerilog
1

Dear Forum,

Is it allowed to redefine a SV interface port direction inside a modport of this interface , i.e :

interface bus_if (input clk); // clk is an input port
  signal my_sig;
  modport master (input  clk, my_sig);
  modport slave  (output clk, my_sig); // clk becames output here
endinterface

Thanks

Jamal

2

You can’t change the directionality of a port that has been defined in the interface declaration. In your example, clk is an input to bus_if and there is no mechanism to change this directionality.

I can’t find anything in the LRM that defines how clk will behave internal to the interface, but I would expect that you would have multiple drivers on clk, or you would get an error.

Three simulators on EDA Playground seem accepting of the code, but I didn’t check the behavior. One simulator gives an error regarding the mismatched directions.