Verification Academy

Topic	Replies	Views	Activity
Uvm_reg: UVM_WARNING: Setting the value of field "xxx" while containing register xxxx is being accessed may result in loss of desired field value UVM UVM , UVM_REG-RACE-CONDITION	6	5012	September 6, 2022
Previous-value of sampling time in SVA SystemVerilog SystemVerilog , assertion , System-Verilog , past , implication , Without-implication	1	566	September 5, 2022
How to integrate a SV reference module UVM UVM , Golden-Reference-Model	1	409	September 5, 2022
Array index concatenation SystemVerilog SystemVerilog , concatenation	1	1409	September 4, 2022
Problem SystemVerilog SystemVerilog	2	521	September 3, 2022
@(posedge "dynamic_string") SystemVerilog SystemVerilog , dynamic	1	512	September 3, 2022
How to pass ENUM type as argument to system Verilog task or function? SystemVerilog SystemVerilog	2	1996	September 3, 2022
Uvm_default_report_server question UVM UVM	3	573	September 3, 2022
Question regarding the 'UVMF Mathworks Integration Users Guide' document UVM UVM	1	296	September 1, 2022
Using a MATLAB generated DUT model in a UVMF testbench UVM UVM	1	453	September 1, 2022
Sampling covergroup when a FSM state ends Coverage Coverage , covergroup	3	764	September 1, 2022
Hi all I have a simple question I couldnt find it in the LRM or anywhere what does this operator (<->) exactly do? SystemVerilog SystemVerilog	5	782	September 1, 2022
Defining Value and Transition bins SystemVerilog SystemVerilog , Defining-Value-and-Transition-bins	3	904	September 1, 2022
Best Scalable Flow For DSP Reference Model Based Verification UVM UVM , UVM-DSP-MATLAB-Verification-referecemodel	1	357	September 1, 2022
Expressing units of time in verification environments UVM UVM , UVM-system-verilog	1	695	August 30, 2022
How to test Injection Error case UVM UVM , error-injection	1	504	August 30, 2022
Constraint failure while using a queue in a task UVM UVM , task , sequence-body , queues-systemverilog	2	602	August 30, 2022
How can I assign one interface to another interface without manually connecting all signals? SystemVerilog SystemVerilog , Interfaces	11	15414	August 30, 2022
4KB concept in AXI SystemVerilog SystemVerilog , AMBA-AXI	1	807	August 30, 2022
How to override instance of class extended from uvm_transaction using "set_inst_override_by_type"? UVM UVM , set_inst_override , UVM_OBJECT-and-UVM_COMPONENT	8	17249	August 30, 2022
Does uvm framework driver supports pipelined sequence item? UVM UVM	0	270	August 30, 2022
Multi thread in DPI-C structure SystemVerilog SystemVerilog , task , dpi-c , multi-thread	2	674	August 30, 2022
Interface with parametrizable number of clock domains SystemVerilog SystemVerilog , assertion , parametrizable-number-of-clocks	1	467	August 29, 2022
Using vips from different vendor UVM UVM , VIP , uvm-testbench-verification	1	432	August 29, 2022
Violation of UVM component name constraints UVM UVM	4	1588	August 29, 2022
What is the use of sequence overrides UVM UVM , override , sequence , set_type_override , uvm_set_inst_override	0	745	August 29, 2022
How m_sequencer identity its sequencer? UVM UVM , m_sequencer	2	482	August 28, 2022
Assertion to check async signals toggling SystemVerilog SystemVerilog	13	1207	August 27, 2022
Task does not work SystemVerilog SystemVerilog	3	915	August 27, 2022
Constraint for selecting multiple byte lanes SystemVerilog SystemVerilog , constraint-randomization , randomization	3	959	August 26, 2022