Hello, I don’t know if my question would be a little silly. But I’m not sure how I could express time in milliseconds and seconds in my uvm verification environment. If for example the specifications tell me:
each frame is 40 ms apart from another. How do I express that 40 ms in units of time in my environment? #nanoseconds=#4e+7?
or how?
or calculate missing frames every second? for instance
Thanks
In reply to Jeffrey_electronic_engineer:
This is quite an involved issue, actually. SystemVerilog has time literals that scales physical time units to a local scale. For example if the local timescale is in picoseconds and you write 40ms, that number gets covered to 40000000. However if you pass that value to code using a different local timescale, for example the UVM package which might have a 1ns timescale, that number gets interpreted as 40 seconds.
It’s usually better to keep your testbech free of time units and think in terms of clock cycles.
repeat (40ms / 4ns) @(posedge clk_250MHz);