Array index concatenation

module m1;
  bit [31:0] mem;
  int i;
  bit [31:0] cmd;
  bit [31:0] addr;
  initial begin
    for (i=1; i<=31; i++)begin
      mem = { addr[31:32-i], cmd[31-i:0] };

when i=1
addr[31], cmd[30:0], total 32 bits used

when i=31
addr[31:1], cmd[0:0], total 32 bits used

Everytime all 32 bits have been used.
But still the code is giving compilation error saying “invalid range/invalid operand”.

Could you please suggest?

Thank You

In reply to Mahesh K:

SystemVerilog does not allow operands with dynamically sized widths. You can creat a mask

bit [31:0] mask;

mask = (32'd1<<i)-32'd1;

mem = addr&~mask | cmd&mask;