@(posedge "dynamic_string")

SystemVerilog
,
1

Hi,

I want to make a dynamic edge trigger as below shape.
Is it possible? If not, please advice me any other workaround.
Thanks.


task automatic chk(input string signal_name);
   begin
     @(posedge $sformatf("Top.duv.%p",signal_name));
        $display("test");
   end
endtask
2

In reply to uvmbee:

SystemVerilog is a compiled programming language, you cannot build references to identifiers using strings. You can pass the entire hierarchical signal name to the task by reference(if the signal is a variable).

task automatic chk(ref bit signal_name);
   begin
     @(posedge signal_name);
        $display("test");
   end
endtask

...
chk(Top.duv.signal);

It the signal is a wire, you can use the bind construct to attach a probe interface to the signal.

See Updated Example Code from DVCon Paper: The Missing Link: The Testbench to DUT Connection | Verification Academy