SystemVerilog is a compiled programming language, you cannot build references to identifiers using strings. You can pass the entire hierarchical signal name to the task by reference(if the signal is a variable).
task automatic chk(ref bit signal_name);
begin
@(posedge signal_name);
$display("test");
end
endtask
...
chk(Top.duv.signal);
It the signal is a wire, you can use the bind construct to attach a probe interface to the signal.