Hi all I have a simple question I couldnt find it in the LRM or anywhere what does this operator (<->) exactly do?

SystemVerilog
1

I saw an interesting constraint solution for generating bitstreams of 1’s and the solution was this foreach(value[i]) i inside {[msb:lsb]} ↔ value[i] == 1 I did not understand the mechanism behind it.

2

In reply to rohandbz:

Section 11.4.7 Logical operators of the LRM explains the logical equivalence (<->) operator.

3

In reply to rohandbz:

If you open up the IEEE 1800-2017 SystemVerilog LRM and search for “<->” you would quickly find this is the logical equality operator. It returns true when the LHS and RHS are either both true or both false.

4

In reply to dave_59:

How different is ↔ from ==

5

In reply to ben@SystemVerilog.us:

  1. ↔ is logical (non-zero or zero true/false) ; == is bitwise or full value comparison (does not matter in this example)
  2. ↔ has much lower precedence than ==. Using == in this example would require adding parenthesis
  3. ↔ has right associatively, == has left.
6

In reply to dave_59:
Thanks so much Dave! looks like I was looking at an older LRM.