Hi all I have a simple question I couldnt find it in the LRM or anywhere what does this operator (<->) exactly do?

[dave_59]

In reply to ben@SystemVerilog.us:

1. ↔ is logical (non-zero or zero true/false) ; == is bitwise or full value comparison (does not matter in this example)
2. ↔ has much lower precedence than ==. Using == in this example would require adding parenthesis
3. ↔ has right associatively, == has left.