Hi all I have a simple question I couldnt find it in the LRM or anywhere what does this operator (<->) exactly do?

[dave_59]

In reply to rohandbz:

If you open up the IEEE 1800-2017 SystemVerilog LRM and search for “<->” you would quickly find this is the logical equality operator. It returns true when the LHS and RHS are either both true or both false.