Interface with parametrizable number of clock domains

SystemVerilog
, ,
1

Hi,

I’m testing a RTL module in system verilog, which has N clock domains, in which, each clock domain has a set of signals associated. (FYI This is my first work with system verilog.)

I created a module interface, composed of N interfaces (declared as an array), each relative to a clock domain. That way, in each clock domain interface I can define a clocking block.

In my test program I used an array of virtual interfaces connected to all clock domains interfaces, so that i can access it’s fields.

Despite I have already tested the module functionality this way, I would like to take more advantage of system verilog assertions.

In my test program i defined properties with ports so that i can check on each clock domain:

property p_1(i);            // clock domain index
  @(vif[i].cb) (a) |-> (b); // vif is the virtual interface array
endproperty

And then, using a generate loop i would assert that property for all clock domains. But this cannot work, since dynamic types (such as virtual) are not allowed in temporal sequences.

generate
  for(genvar i=0; i < NCLKS; i++) begin: assert_GEN
    chk_1: assert property(p_1(i));
  end
endgenerate
2

In reply to vandoren:

Yes, the problem is that vif[i] starts out as null reference. But you should be able to use the actual interface instance with a little restructuring.

property p_1(cb);            // clock domain index
  @(cb) (a) |-> (b); // vif is the virtual interface array
endproperty

 for(genvar i=0; i < NCLKS; i++) begin: assert_GEN
    chk_1: assert property(p_1(path_to_interface[i].cb));
  end