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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.

    • Languages & Standards

      • Portable Test and Stimulus
      • Functional Safety
      • Design & Verification Languages

    • Methodologies

      • UVM - Universal Verification Methodology
      • UVM Framework
      • UVM Connect
      • FPGA Verification
      • Coverage

    • Techniques & Tools

      • Verification IQ
      • Verification IP
      • Static-Based Techniques
      • Simulation-Based Techniques
      • Planning, Measurement, and Analysis
      • Formal-Based Techniques
      • Debug
      • Acceleration
  • All Courses
    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.

    • Universal Verification Methodology (UVM)

      • Introduction to UVM
      • UVM Basics
      • Advanced UVM
      • UVM Connect
      • UVM Debug
      • UVMF - One Bite at a Time

    • Featured Courses

      • Introduction to ISO 26262
      • Introduction to DO-254
      • Clock-Domain Crossing Verification
      • Portable Stimulus Basics
      • Power Aware CDC Verification
      • Power Aware Verification
      • SystemVerilog OOP for UVM Verification

    • Additional Courses

      • Assertion-Based Verification
      • An Introduction to Unit Testing with SVUnit
      • Evolving FPGA Verification Capabilities
      • Metrics in SoC Verification
      • SystemVerilog Testbench Acceleration
      • Testbench Co-Emulation: SystemC & TLM-2.0
      • Verification Planning and Management
      • VHDL-2008 Why It Matters

    • Formal-Based Techniques

      • Formal Assertion-Based Verification
      • Formal-Based Technology: Automatic Formal Solutions
      • Formal Coverage
      • Getting Started with Formal-Based Technology
      • Handling Inconclusive Assertions in Formal Verification
      • Sequential Logic Equivalence Checking

    • Analog/Mixed Signal

      • AMS Design Configuration Schemes
      • Improve AMS Verification Performance
      • Improve AMS Verification Quality
  • All Forum Topics
    The Verification Community is eager to answer your UVM, SystemVerilog and Coverage related questions. We encourage you to take an active role in the Forums by answering and commenting to any questions that you are able to.

    • UVM Forum

      • Active Questions
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      • UVM Forum

    • SystemVerilog Forum

      • Active Questions
      • Solutions
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      • SystemVerilog Forum

    • Coverage Forum

      • Active Questions
      • Solutions
      • Replies
      • No Replies
      • Search
      • Coverage Forum

    • Additional Forums

      • Announcements
      • Downloads
      • OVM Forum
  • Patterns Library
    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).

    • Implementation Patterns

      • Environment Patterns
      • Stimulus Patterns
      • Analysis Patterns
      • All Implementation Patterns

    • Specification Patterns

      • Occurrence Property Patterns
      • Order Property Patterns
      • All Specification Patterns

    • Pattern Resources

      • Start Here - Patterns Library Overview
      • Whitepaper - Taking Reuse to the Next Level
      • Verification Horizons - The Verification Academy Patterns Library
      • Contribute a Pattern to the Library
  • All Cookbooks
    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.

    • UVM Cookbook

      • UVM Basics
      • Testbench Architecture
      • DUT-Testbench Connections
      • Configuring a Test Environment
      • Analysis Components & Techniques
      • End Of Test Mechanisms
      • Sequences
      • The UVM Messaging System
      • Other Stimulus Techniques
      • Register Abstraction Layer
      • Testbench Acceleration through Co-Emulation
      • Debug of SV and UVM
      • UVM Connect - SV-SystemC interoperability
      • UVM Versions and Compatibility
      • UVM Cookbook

    • Coding Guidelines & Deployment

      • Code Examples
      • UVM Verification Component
      • Package/Organization
      • Questa/Compiling UVM
      • SystemVerilog Guidelines
      • SystemVerilog Performance Guidelines
      • UVM Guidelines
      • UVM Performance Guidelines

    • Coverage Cookbook

      • Introduction
      • What is Coverage?
      • Kinds of Coverage
      • Specification to Testplan
      • Testplan to Functional Coverage
      • Bus Protocol Coverage
      • Block Level Coverage
      • Datapath Coverage
      • SoC Coverage Example
      • Requirements Writing Guidelines
      • Coverage Cookbook
  • All Events
    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.

    • Featured & On-Demand

      • RISC-V Design - Webinar
      • Exploring Formal Coverage
      • Processor Customization
      • Interconnect Formal
      • Formal and the Next Normal
      • Formal Verification Made Easy
      • Data Independence and Non-Determinism
      • Exhaustive Scoreboarding
      • Visualizer Debug Environment
      • Webinar Calendar

    • On-Demand Library

      • SystemVerilog Assertions
      • Practical Flows for Continuous Integration
      • Continuous Integration
      • Questa Verification IQ
      • Avery & Siemens VIP
      • Protocol and Memory Interface Verification
      • HPC Protocols & Memories
      • Preparing for PCIe 6.0: Parts I & II
      • High Defect Coverage
      • SoC Design & Functional Safety Flow
      • Complex Safety Architectures
      • All On-Demand Recordings

    • Recording Archive

      • Lint vs Formal AutoCheck
      • FPGA Design Challenges
      • Design Solutions as a Sleep Aid
      • Fix FPGA Failures Faster
      • CDC and RDC Assist
      • The Dog ate my RTL
      • Questa Lint & CDC
      • Hierarchical CDC+RDC
      • Improving Initial RTL Quality
      • CDC Philosophy
      • Hardware Emulation Productivity
      • The Three Pillars of Intent-Focused Insight
      • All Webinar Topics

    • Conferences & WRG

      • 2022 Functional Verification Study
      • Improving Your SystemVerilog & UVM Skills
      • Automotive Functional Safety Forum
      • Aerospace & Defense Tech Day
      • Siemens EDA Functional Verification
      • Industry Data & Surveys
      • DVCon 2023
      • DVCon 2022
      • DVCon 2021
      • Osmosis 2022
      • All Conferences

    • Siemens EDA Learning Center

      • EDA Xcelerator Academy(Learning Services) Verification Training, Badging and Certification
      • View all Xcelerator Academy classes
  • About Verification Academy
    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.

    • Blog & News

      • Verification IQ
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      • Verification Horizons - July 2023
      • Verification Horizons - March 2023
      • Verification Horizons - December 2022
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  • Home
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  • UVM Debug

UVM Debug

UVM Debug Course | Subject Matter Expert - Tom Kiley | Universal Verification Methodology Topic

Design complexity continues to increase, which is contributing to new challenges in verification and debug. Fortunately, new solutions and methodologies (such as UVM) have emerged to address growing design complexity. Yet, even with the productivity gains that can be achieved with the adoption of UVM, newer debugging challenges specifically related to UVM need to be addressed.

In this course, we examine common UVM debug issues, and provide a systematic set of recommendations to effectively address them.

Harry Foster
Tom Kiley
Simulation-Based Techniques UVM - Universal Verification Methodology
Walk

Featured Session

Are You Trapped in an Unfamiliar, Large SystemVerilog UVM Testbench?

Are You Trapped In an Unfamiliar, Large SystemVerilog UVM Testbench? | User2User - Munich 2017

This session will describe useful debug techniques for debugging a UVM testbench with 8 to 10 agents, and many stimulus generators, checkers and exception handlers running in parallel.

Upcoming Sessions

  • Debugging UVM Scoreboards
  • Debugging Objections
  • Using Breakpoints for UVM Debug
  • UVM PostSim Debug in Wave Window

Sessions

UVM Debug Editor Insight

Verification Academy Editor Insight Session | Subject Matter Expert - Harry Foster | UVM Debug Course

This editor insight session provides an historical perspective on the origin of the word debugging, followed by a discussion on industry trends that motivated us to create our new UVM debug course.

UVM Connectivity Debug

UVM Connectivity Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will discuss how to debug connectivity issues between UVM components using the UVM Schematic viewer.

UVM Phase Debug

UVM Phase Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will provide an overview of UVM phases, some of the common issues that users run into, and methods to effectively debug them.

Memory Leak Debug

Memory Leak Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will describe what a memory leak is in a UVM environment and how to effectively debug the issue.

UVM Configuration Database Debug

UVM Configuration Database Debug Session | Subject Matter Expert - Tom Kiley | UVM Debug Course

In this session we will provide an overview of the UVM configuration database, discuss some of the common issues with configurations, and methods to debug them.

Visualizer™ Debug Environment

Find bugs faster in the Visualizer™ Debug Environment, a high-performance, high-capacity debugger. Tightly integrated with both Questa Simulation and Veloce Emulation, Visualizer provides a full set of synchronized views that analyze waveforms, source code, connectivity and more for Verilog, SystemVerilog, VHDL and SystemC. In addition to being very intuitive and easy to use, Visualizer has several powerful features that improve debug productivity for SystemVerilog/UVM, transaction-level, RTL, gate-level and low-power design and verification.

Features

  • Automatic X Tracing in Your Design
  • Wave Windows Features
  • FSM Viewer
  • Driver and Receiving Tracing
  • Design Exploration with the Advanced Search Window
  • Adding Signals to the Wave Window

Debugging Testbench in Interactive Mode

The following videos cover major features of Visualizer Interactive Mode. It might be useful to view them in the following order:

  • Part 1: Invoking Visualizer
  • Part 2: Intro to Commonly Used Windows
  • Part 3: Set Breakpoints and Single Step Debug
  • Part 4: Viewing Data Values
  • Part 5: Navigating a UVM Testbench
  • Part 6: Navigation with Class and File Views
  • Part 7: RTL Interactive Debug
  • Part 8: Checkpoint/Restore


SystemVerilog & UVM Training

Featured On-Demand SystemVerilog & UVM Classes:

  • SystemVerilog Vectors and Arrays
  • SystemVerilog Advanced OOP
  • SystemVerilog Functional Coverage
  • UVM Transactions and Sequences
  • UVM Monitors and Agents
  • UVM Tests and Complex Sequences

Please visit the Functional Verification Library to find the learning path to improve your verification skills.

SystemVerilog Instructor-led Training:

  • SystemVerilog Assertions
  • SystemVerilog UVM
  • SystemVerilog UVM Advanced
  • SystemVerilog for Verification

Please visit the Learning Center to find a class scheduled in your region for additional training.

Verification Consulting Services:

  • Testbench Acceleration
  • Audit-Ready Verification
  • Independent Verification
  • Cloud-Based Regression
  • Advanced Verification Flows

Contact Mentor Consulting Services to learn more.

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