Debugging in UVM

UVM
1

For debugging purpose,how to print messages that indicates the components phase

2

Hi pmehro,

Excerpt from “SV and UVM debug” section of UVM cookbook. Hope this helps you.

Phasing in UVM can be complicated with multiple phases running in parallel. To help understand when a phase starts
and ends, the UVM Command Line Processor can be used to enable a trace with the +UVM_PHASE_TRACE plusarg.
When this plusarg is added to the simulator command line, it results in output similiar to this:

UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1364) @ 0 ns: reporter [PH/TRC/SCHEDULED]

Phase ‘common.run’ (id=93) Scheduled from phase common.start_of_simulation

UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1114) @ 0 ns: reporter [PH/TRC/STRT] Phase

‘common.run’ (id=93) Starting phase

UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1364) @ 0 ns: reporter [PH/TRC/SCHEDULED]

======

Thanks,
Rajkumar.

3

In reply to S.P.Rajkumar.V:

Hi pmehro,
Excerpt from “SV and UVM debug” section of UVM cookbook. Hope this helps you.
=====
Phasing in UVM can be complicated with multiple phases running in parallel. To help understand when a phase starts
and ends, the UVM Command Line Processor can be used to enable a trace with the +UVM_PHASE_TRACE plusarg.
When this plusarg is added to the simulator command line, it results in output similiar to this:

UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1364) @ 0 ns: reporter [PH/TRC/SCHEDULED]

Phase ‘common.run’ (id=93) Scheduled from phase common.start_of_simulation

UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1114) @ 0 ns: reporter [PH/TRC/STRT] Phase

‘common.run’ (id=93) Starting phase

UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1364) @ 0 ns: reporter [PH/TRC/SCHEDULED]

======
Thanks,
Rajkumar.

Hi Rajkumar,
with this switch , whatever information UVM gives is not clear.

This doesnt display whether build phase is called from env , agen, driver or scorboard !!

Lets say we need to check the phase execution flow for different components,is there any option?

I mean , lets say I want to check whether build phase does a top-down approach,I actually need to insert the print statements inside every component…

Is there any option which will show me whether build is called from test, build is called from scorebord and so on?

thanks,
Suyog

4

In reply to pmehro:

If you do not use the sub-phases of the run_phase it is quite easy.
run_phase is where the execution takes place. All the other phases are went through to establish the UVM environment.
You can easily issue in each of these phase like build_phase/connect_phase etc a `uvm_info.

5

In reply to sree205:
The UVM has no way of knowing if you have provided an override to a phase for any component, and there is no callback mechanism for the execution of each components phase method.

Some options I can think of are:

  • Use your tools interactive tracing or break-pointing features to see how the phases in your components execute
  • create an extension to uvm_component that all your components are derived from that instruments the messages you need to see.
  • Modify the the UVM library (most likely uvm_phase) and instrument it with the messages you need