Debugging in UVM

UVM
2

Hi pmehro,

Excerpt from “SV and UVM debug” section of UVM cookbook. Hope this helps you.

Phasing in UVM can be complicated with multiple phases running in parallel. To help understand when a phase starts
and ends, the UVM Command Line Processor can be used to enable a trace with the +UVM_PHASE_TRACE plusarg.
When this plusarg is added to the simulator command line, it results in output similiar to this:

UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1364) @ 0 ns: reporter [PH/TRC/SCHEDULED]

Phase ‘common.run’ (id=93) Scheduled from phase common.start_of_simulation

UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1114) @ 0 ns: reporter [PH/TRC/STRT] Phase

‘common.run’ (id=93) Starting phase

UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1364) @ 0 ns: reporter [PH/TRC/SCHEDULED]

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Thanks,
Rajkumar.