In reply to S.P.Rajkumar.V:
Hi pmehro,
Excerpt from “SV and UVM debug” section of UVM cookbook. Hope this helps you.
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Phasing in UVM can be complicated with multiple phases running in parallel. To help understand when a phase starts
and ends, the UVM Command Line Processor can be used to enable a trace with the +UVM_PHASE_TRACE plusarg.
When this plusarg is added to the simulator command line, it results in output similiar to this:
UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1364) @ 0 ns: reporter [PH/TRC/SCHEDULED]
Phase ‘common.run’ (id=93) Scheduled from phase common.start_of_simulation
UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1114) @ 0 ns: reporter [PH/TRC/STRT] Phase
‘common.run’ (id=93) Starting phase
UVM_INFO …/uvm-1.1a/src/base/uvm_phase.svh(1364) @ 0 ns: reporter [PH/TRC/SCHEDULED]
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Thanks,
Rajkumar.
Hi Rajkumar,
with this switch , whatever information UVM gives is not clear.
This doesnt display whether build phase is called from env , agen, driver or scorboard !!
Lets say we need to check the phase execution flow for different components,is there any option?
I mean , lets say I want to check whether build phase does a top-down approach,I actually need to insert the print statements inside every component…
Is there any option which will show me whether build is called from test, build is called from scorebord and so on?
thanks,
Suyog