SystemC continues to be used for virtual prototyping, one key values is performance. Performance that enables early validation of firmware in parallel with architecture. The release of the TLM2 standard enables many new technologies; co-emulation is a major beneficiary. As you move from an untimed high level architectural model to the more detailed RTL representation of your virtual prototype, performance drop-off is expected. With co-emulation you can regain the performance needed to do system level tasks as you did in your virtual prototype environment.
This course advocates that functional verification through modern SystemC testbenches paired with co-emulation enables further verification productivity improvements in terms of raw performance. SystemC simulation combined with co-emulation will deliver dramatic speedup of execution of verification. This course on Acceleration of SystemC and TLM-2.0 testbenches with Co-Emulation will give you the confidence required to start the process of investigating and creating a single testbench environment that can be used for both simulation as well as hardware-assisted acceleration.
This course consists of approximately 1.5 hours of content, and is divided into six sessions of average 15 minutes each. The course is primarily aimed at existing SystemC H/W engineers or managers who recognize they have a functional verification throughput problem but have little or no experience with using emulation as a means for accelerating high level testbench environments. This course may also be of interest to S/W engineers who demand earlier access to systems for S/W development.
You are encouraged to first view Evolving Verification Capabilities by Harry Foster that provides the framework for all of the Academy courses, then the recommended prerequisites; Acceleration of SystemVerilog Testbenches, Verification Planning and Management.