Jim Lewis

Jim Lewis, the founder of <a href="http://www.synthworks.com/index.htm" target= "_blank">SynthWorks</a>, has twenty-eight years of design, teaching, and problem solving experience. In addition to working as a Principal Trainer for SynthWorks, Mr. Lewis does ASIC and FPGA design, custom model development, and consulting. Mr. Lewis was previously employed with Zycad's Protocol division where he worked as an on-site VHDL trainer, methodology consultant, and ASIC designer. As a representative from Zycad, he provided VHDL training, methodology consulting, and ASIC design for Lockheed Sanders in their development of 22 ASICs for the F22 program. On another assignment for Zycad, he worked as a VHDL trainer, Synopsys synthesis trainer, problem solver, and ASIC designer for SGS Thomson in their development of a Video Codec chip. In addition to other responsibilities, Mr. Lewis acted as an on-site focal point for resolving VHDL synthesis issues for both companies.

Mr. Lewis was also employed by TRW where he designed ASICs, FPGAs, and worked as a member of their VHDL Methodology Development Group. Mr. Lewis, who holds a BSEE/BSCEE and MSEE from Purdue University, is a member of the IEEE and the Eta Kappa Nu, and Tau Beta Pi Honor Societies. Mr. Lewis is chair of the IEEE 1076 VHDL Analysis and Standardization Working Group (VASG) and is an active member in IEEE and Accellera's VHDL standardization efforts. Mr. Lewis is also co-author of <a href="http://www.amazon.com/VHDL-2008-Stuff-Systems-Silicon/dp/0123742498" title="VHDL-2008: Just the New Stuff" target="_blank">VHDL-2008: Just the New Stuff</a> and recommends <a href="http://www.amazon.com/Designers-Guide-Edition-Systems-Silicon/dp/0120887851" title="The Designer’s Guide to VHDL" target="_blank">The Designer’s Guide to VHDL</a> and the <a href="http://standards.ieee.org/findstds/standard/1076-2008.html" title="VHDL-2008 LRM" target="_blank">VHDL-2008 LRM</a>.

Content by Jim Lewis

VHDL-2008 Why It Matters
VHDL 2008 Jan 17, 2013 Jim Lewis Track

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

VA Live: Silicon Valley

Thursday, Jan 30th-9:30 AM PST

Verification IP for UCIe, PCIe Gen 7, HBM4, and more

Formal Security Webinar

Wednesday, Feb 05th-8:00 AM PST

Explore How to Protect Against Data Corruption with Formal Security Verification

FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Simulation Webinar

Wednesday, Jan 15th-8:00 AM PST

Unlocking the Power of QuestaSim and Visualizer Integration

Jim Lewis

Content by Jim Lewis

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VHDL-2008 Why It Matters

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