Hans Van Der Schoot

Dr. Hans van der Schoot is a recognized specialist in verification technology, and employed as a methodologist in the Emulation Division at Siemens EDA. Hans has a solid background and wealth of knowledge in functional verification from his many years as a researcher, engineer and consultant in the field, with extensive practical experience providing verification methodology and implementation consulting and training services in the industry. He has authored multiple papers pertinent to hardware verification and software testing. Hans obtained his doctorate degree in computer science from the University of Ottawa, Canada, after graduating from the University of Twente in the Netherlands, also in computer science. Prior to joining Siemens EDA, he was the Vice President Engineering at XtremeEDA. He has also worked independently as an expert design verification consultant, following senior engineering positions with Qualis Design, PMC-Sierra, and Nortel Networks.

Content by Hans Van Der Schoot

SystemVerilog Testbench Acceleration
Acceleration Feb 25, 2011 Hans Van Der Schoot Track

New UVMF Release

The UVM Framework (UVMF) provides a jump-start for learning UVM and building UVM verification environments.

Missing Forum Notifications?

Check out this blog post from Dave Rich on how to enable Forum Notifications.

Upcoming VIQ Webinar

Thursday, Nov 21st-8:00 AM PST

Boost Your Verification Productivity with Questa Verification IQ

On-Demand HBM4 Webinar

Verifying the Next Generation High Bandwidth Memory Controllers for AI and HPC Applications

Upcoming FPU Webinar

Wednesday, Jan 22nd-8:00 AM PST

Streamlining FPU Verification with an Alternative to C-reference Model Approaches

Hans Van Der Schoot

Content by Hans Van Der Schoot

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