Verification Academy

Topic	Replies	Views	Activity
How do I define an associative array of queues? SystemVerilog SystemVerilog , associative-array , Queues-in-system-verilog , systemverilog-Arrays	15	15297	August 19, 2022
Can we use system verilog properties/assertions inside a class? SystemVerilog SystemVerilog , system-verilog-assertion-SVA	13	16175	October 22, 2019
Config_db - parameters for set/get method UVM UVM , config_db	28	11185	February 19, 2020
Package export does not work like I expect SystemVerilog SystemVerilog	14	14680	April 8, 2022
Timescale and Timeunit SystemVerilog SystemVerilog	11	16366	September 19, 2019
What is the best way to get a randomized real value? SystemVerilog SystemVerilog	9	17678	October 14, 2022
Regarding Race Condition SystemVerilog SystemVerilog	10	16817	March 14, 2023
How to change random seed using command line parameter SystemVerilog SystemVerilog	9	17102	September 25, 2015
Counting number of events on clock a, while clock o is forbidden SystemVerilog SystemVerilog , assertion , first_match	24	10786	May 16, 2015
SystemVerilog Checker SystemVerilog SystemVerilog , system-verilog-checker	9	16770	July 20, 2020
[SVA] signal rises and stays stable check -> how to write an assertion? SystemVerilog SystemVerilog	20	11153	May 24, 2019
Interview question on constraint SystemVerilog SystemVerilog , constraints , uvm-sv-constraints	22	10646	April 15, 2023
Constraint for one hot encoded vectors in SV SystemVerilog SystemVerilog	18	11514	August 2, 2023
What is meant by a static class? SystemVerilog SystemVerilog	11	14226	July 15, 2019
Problem in unique of Constraint Randomization SystemVerilog SystemVerilog , constraint , unique	13	12879	April 29, 2016
How to check that a Signal was NEVER HIGH or NEVER RISE during the simulation? SystemVerilog SystemVerilog , never-rise , never-high	21	10212	March 25, 2017
Can the monitor communicate with the sequence directly? UVM UVM , driver , TLM-ports , Generating-sequences	17	11176	December 7, 2021
SV Assertions for Arbiter priority SystemVerilog SystemVerilog , assertion , Arbiter-priority	12	13028	April 25, 2020
Working with multi-dimensional associative arrays SystemVerilog SystemVerilog , multi , dimensional , associative	11	13496	May 6, 2014
Best way to introduce delay between sequences UVM UVM , sequence-delays	19	10270	May 24, 2019
Clock Frequency Checker SystemVerilog SystemVerilog , clock-frequency	12	12600	February 24, 2021
Can i convert UVM_ERRORs to UVM_INFO or UVM_WARNING based on id? UVM UVM , convert , uvm_error , uvm_info , uvm_warning	9	14068	December 13, 2013
Printing associative array SystemVerilog SystemVerilog , associative-array	9	13929	February 21, 2023
How to Sample data during Functional Coverage? Coverage Coverage , function-coverage , ignore-sampled-coverage-conditionaly-later	9	13907	October 10, 2017
UVM UVM UVM	71	5114	August 3, 2018
Use of regular expression for string comparison UVM UVM , regular-expressions	9	13441	May 19, 2021
Necessity of writing 'include "uvm_macros.svh" UVM UVM , uvm_macrossvh	12	11358	March 1, 2024
How to delete duplicate elements from associative array and Queue in System Verilog SystemVerilog SystemVerilog , associative-array , accessing-the-associative-array-elements	15	9873	August 23, 2019
Near "uvm_sequence_item": syntax error, unexpected IDENTIFIER UVM UVM	25	7702	August 2, 2017
Burst Transfer SystemVerilog SystemVerilog , BURST-Transfer-AHB	9	12352	September 5, 2018
“static task” vs. “task static” SystemVerilog SystemVerilog , static-task-method	14	10027	April 2, 2016
Not registered with the factory UVM UVM	10	11638	January 15, 2024
SVA evaluation SystemVerilog SystemVerilog	12	5820	March 25, 2022
Override parameters in SV package SystemVerilog SystemVerilog	9	11692	August 10, 2023
Why we should use non-blocking assignments in driver and blocking assignments in monitor? UVM UVM	13	9829	July 19, 2023
Can I trigger an event in one agent and after triggered, do something inside another agent? UVM UVM , uvm_event , multiple-agent , uvm_event_pool , trigger , event-trigger	14	9490	December 27, 2017
Prime numbers constraint SystemVerilog SystemVerilog	12	10030	January 4, 2024
Dumping vcd files in a UVM test UVM SystemVerilog , UVM , VCD , vcd_files , dumpfile	12	9978	March 4, 2015
Random associative array SystemVerilog SystemVerilog	17	8295	October 12, 2022
Magic square on system verilog SystemVerilog SystemVerilog	18	4416	January 18, 2024
Exclude data from $urandom_range SystemVerilog SystemVerilog , randomization , urandom_range	9	10822	June 21, 2019
Specifying "ignore_bins = <everything else>" in coverpoint bins Coverage Coverage	9	10733	January 30, 2020
Stoping a sequencer and starting it again in UVM UVM UVM , sequence , sequncer	13	9016	June 16, 2016
Clock generation through UVC UVM UVM , uvc , clock	15	8233	March 9, 2022
Error-[TMAFTC] Too many arguments to function/task call UVM UVM , Compile-UVM-12-in-Windos-64-bit	12	8819	July 18, 2018
Assertion stable after two or more rising edge UVM UVM , assertion , fell , stable	11	9136	March 28, 2017
VHDL record to Systemverilog struct SystemVerilog SystemVerilog , vhdl-record-struct-mapping	11	9119	July 1, 2014
Can we sample coverpoints which are design parameters? Coverage Coverage	14	8080	February 8, 2019
RAL Backdoor access UVM UVM	14	7996	August 23, 2016
How to find all indices of an associative array SystemVerilog SystemVerilog	9	9580	April 17, 2016