Latest UVM topics - Verification Academy

Topic	Replies	Views	Activity
About the UVM category	0	348	January 1, 2023
Configuring property using Field Automation macro UVM , uvm_config_db , field-macros	1	14	May 18, 2024
Uvm_config_db set method clarification UVM , uvm_config_db	1	102	May 17, 2024
Execution of connect phase twice in simulation UVM , UVM-phases , phase-jump	14	2027	May 17, 2024
RAL Register access RAL	3	46	May 16, 2024
Issue with RAL Coverage bins creation UVM , uvm-ral , ral_coverage	3	28	May 16, 2024
How to disable auto predict for a specific register read operation?	1	30	May 16, 2024
How to break/disable FOREVER BEGIN LOOP	2	35	May 15, 2024
Skipping a register field from comparison with RAL RAL , uvm_ral , RAL-UVM	10	115	May 15, 2024
Is it possible to treat RAL as static database such that I can access it in assertion checker	0	19	May 14, 2024
Instantiate a uvm class in another class but not to run uvm_phases of class	2	34	May 11, 2024
About new tech learning SystemVerilog , UVM	0	38	May 10, 2024
Start AHB sequence based on AXI sequence response UVM	0	38	May 10, 2024
Does uvm_config_db pass by value or pass by reference?	1	41	May 9, 2024
Set_type_override gives compile error set_type_override	3	32	May 8, 2024
Subordinated driver in agent UVM	4	39	May 7, 2024
Why does the RAL read() update the mirrored AND desired register model values? UVM , uvm-ral , Ral-write-and-read-methhods	3	2970	May 6, 2024
How can we verify a memory whose address location is swapped UVM , memory-verification	19	10741	May 5, 2024
Uvm_sequencer usage UVM	2	52	May 5, 2024
Seq_item_port driver-sequencer - communication issue	2	45	May 5, 2024
UVM Monitor the interface output, don't use the driver transaction - understanding this training recommendation UVM , uvm-driver-monitor-transaction	2	169	May 4, 2024
While i am using backdoor access for memory model i am able to writing the data into memory while reading the data from back door throug uvm ral i am getting error as either path is invalid or you dont have PLI/ACC visibility for that object UVM	1	40	May 4, 2024
Overriding UVM_NONE messages UVM-Reporting	4	43	May 4, 2024
Coverage collector or subscriber usage UVM , Coverage	0	61	May 4, 2024
Overriding a parameter UVM , parameter-override-class	9	14775	May 1, 2024
Uvm sequence body does not start after completion of base sequence pre_body	3	50	May 1, 2024
Uvm_reg_data_t constraint randomization	2	50	May 1, 2024
Analysis Port Write functionality analysis-port , analysis-export	1	40	April 30, 2024
How to cover unsigned int SystemVerilog , UVM , Coverage	1	68	April 30, 2024
Clarifications about uvm_config db performance	3	72	April 26, 2024