Using goto repetition
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4
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280
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May 4, 2024
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Discrepancy on legality of the consequent
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7
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58
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May 4, 2024
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Smart way to bundle up multiple RTL signals when passing to monitor
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1
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27
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May 2, 2024
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Randc variable randomization inside top sequence class
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3
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26
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May 1, 2024
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How to cover unsigned int
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1
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41
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April 30, 2024
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SystemVerilog Hiearchial Reference to UUT Internal Signal?
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2
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26
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April 30, 2024
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System verilog inheritance for sequences
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4
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32
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April 30, 2024
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Using sequence method triggered within Sampled value functions
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5
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74
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April 27, 2024
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How can you set order for the execution of initial begin blocks without using event or wait statements?
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1
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27
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April 27, 2024
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How text macro affect inside and outside pkg?
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2
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26
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April 27, 2024
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Performance problem
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3
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58
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April 24, 2024
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Constraint Randomization Interview Question
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17
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4289
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April 24, 2024
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Vopt-13412) Virtual methods of an object or built-in method are not allowed in event control expressions
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1
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29
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April 23, 2024
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Arr.sum() - constraint
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1
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60
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April 23, 2024
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What is the general difference between static and dynamic events in SystemVerilog?
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3
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914
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April 23, 2024
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N Queen Board Problem in SV Constraint
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7
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602
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April 23, 2024
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How to pass delay through a variable in assertion
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7
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2017
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April 23, 2024
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Empty bin warning for disabled cover point
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1
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38
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April 19, 2024
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Elaboration time constant for enumerated type.num()
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2
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35
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April 18, 2024
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Parameter type in interface
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1
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43
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April 16, 2024
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[UVM/REG/DUPLROOT] There are 2 root register models named "reg_model". The names of the root register models have to be unique
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1
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983
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April 16, 2024
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Illegal range in part select
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10
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4776
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April 16, 2024
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APB state operation
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0
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34
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April 15, 2024
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NO HANDLE OF VIRTUAL INTERFACE IS RECEIVED
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5
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361
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April 15, 2024
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Constraint array
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2
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95
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April 12, 2024
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Function New Constructor
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1
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59
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April 11, 2024
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How do I avoid using #0 in an interface monitor
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3
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70
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April 10, 2024
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How the within syntax is working in SVA
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7
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2191
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April 10, 2024
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System Verilog Fine grain Process
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2
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72
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April 9, 2024
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Backdor access without using RAL model
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3
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70
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April 8, 2024
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