For the purpose of our proof-of-concept, we are using a Zetta-Hz High Speed CDMA Transceiver and running standard simulation with coverage and then comparing with results attained using automation.
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Figure 1 - Zetta-Hz High Speed CDMA Transceiver
DESCRIPTION OF THE DUT
This Zetta-Hz High Speed CDMA Transceiver is designed for multiple access by multiple users at a time by spreading and de-spreading of codes with ultra-high speed networking communication using different CDMA techniques such as DSSS (Direct sequence spread spectrum), frequency hopping, Chaotic, etc. The design does data transmission and reception in parallel for various data interface cards of differing high speed data transfer rates. In this design, transmission and reception are done by different PRBS data pattern sequences like PRBS7, PRBS10, PRBS15, PRBS23, PRBS31, PRBS48, PRBS52, PRBS63, etc., as per the ITU standard.
The Zetta-hertz transceiver consists of a zetta clock frequency oscillator/generator, channel encoder, modulator, wireless channel, demodulator, decoder, and PRBS-pseudo noise carrier frequency wave generator. The zetta hertz oscillator generates one complete zetta hertz clock cycle with 2^70/2 low and 2^70/2 high clock pulses. Total clock frequency cycle is 2^70 clock pulses. This clock frequency is input to all CDMA blocks, and generates high frequency baud rates in terms of Zetta-hertz clock frequency. All these blocks are synchronized with Zetta-hertz clock frequency rate.
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Figure 2 - N-bit Pseudo random binary sequence generator
To verify the Zetta-Hertz CDMA Transceiver, we use a UVM-based verification environment. The hierarchical structure of UVM testbench as shown in Figure 3.
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Figure 3 - Hierarchical structure of UVM
CONSTRAINED RANDOM VERIFICATION AND FUNCTIONAL COVERAGE
Using the standard simulation technique only the critical states can be hit. Constrained randomization hits these states in unpredictable ways. Often constrained randomization repeats states and may miss the coverage points. Bugs may be in the hidden/uncovered nodes and may not be detected by the constrained random verification.
The coverage matrix is shown in Figure 4 with standard simulation which shows percentage as 35.41%, as seen in Figure 5.
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Figure 4 - Hierarchical structure of UVM
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Figure 5 - Functional Coverage with standard simulation
Coverage matrix using Automation tool:
As we will see, the coverage can be increased by applying automation to the creation of test scenarios. First, the automation tool imports the UVM testbench, including the sequence items and scoreboard so the tool has access to the covergroups and stimulus items.
//Sequence Item
class zetta_cdma_seq_item extends uvm_sequence_item;
`uvm_object_utils(zetta_cdma_seq_ite m)
reg reset;
rand reg [2:0] prbstype;
rand reg [3:0]
prbs_cdma;
_channel_sel;
rand reg [9:0] serin;
reg cdmatxserout;
reg[9:0] cdmarxserout;
reg [63:0]cdmatxparout;
reg [63:0] cdmarxparout;
function new (string name = "zetta_cdma_seq_item");
super.new(name);
endfunction
........
endclass |
Zetta_sequence_item code:
//SCOREBOARD
Class zetta_cdma_scoreboard extends uvm_scoreboard;
`uvm_component_utils(zetta_cdma_scor eboard)
uvm_tlm_analysis_fifo#(zetta_cdma_se q_item) zetta_imp;
zetta_cdma_seq_item xtn;
covergroup zetta_cover;
option.per_instance=1;
TXSER: coverpoint xtn.cdmatxserout{ bins all = {0,1};}
PRBSTYPE: coverpoint xtn.prbstype;
CHANNEL: coverpoint xtn.prbs_cdma_channel_sel;
SERIN: coverpoint xtn.serin;
RXSER: coverpoint xtn.cdmarxserout { bins low = {[0:100]};}
TXPAR: coverpoint xtn.cdmatxparout{ bins low = {[0:50]};}
RXPAR: coverpoint xtn.cdmarxparout{ bins low = {[0:100]};}
CROSS: cross xtn.prbstype,xtn.prbs_cdma_channel_s el,xtn.serin;
endgroup
function new(string name,uvm_component parent);
super.new(name,parent);
zetta_imp=new("zetta_imp",this); zetta_cover =new();
endfunction
function void build_phase(uvm_phase phase);
super.build_phase(phase);
endfunction
task run_phase(uvm_phase phase);
forever begin
zetta_imp.get(xtn);
`uvm_info(get_type_name(),$sformatf( "SCOREBOARD
%s",xtn.sprint),UVM_MEDIUM);
zetta_cover.sample();
end
endtask
endclass |
Zetta_scoreboard code:
After several steps, the tool generates a UVM sequence. Source code of the tool generated sequence is shown in below.
//GENERATED UVM SEQUENCE
`define INCLUDED_zetta_cdma_sequence_gen_SVH import uvm_pkg::*;
`include "uvm_macros.svh"
`include "zetta_cdma_sequence_gen_scheduler.svh"
`include "zetta_cdma_sequence_gen_items.svh"
`include "zetta_cdma_sequence_gen_zetta_cover 1.svh"
`include "zetta_cdma_sequence_gen_callback_cl osures.svh"
typedef zetta_cdma_sequence zetta_cdma_sequence_gen_base_t;
typedef class zetta_cdma_sequence_gen_cb;
class zetta_cdma_sequence_gen extends zetta_cdma_sequence_gen_base_t;
typedef zetta_cdma_sequence_gen zetta_cdma_sequence_gen_t;
`uvm_object_utils(zetta_cdma_sequenc e_gen)
zetta_cdma_sequence_gen_scheduler m_scheduler;
zetta_cdma_sequence_gen_cb m_te
Callback;
zetta_cdma_seq_item m_zetta_cdma_seq_item_inst;
zetta_cdma_sequence_gen_pc_closure #(zetta_cdma_sequence_gen_t) m_pc_closure;
zetta_cdma_sequence_gen_zetta_cover1 m_zetta_cdma_sequence_gen_zetta_cover1;
function new(string name="");
super.new(name);
endfunction
virtual task body();
m_scheduler = new(get_full_name());
register_actions();
create_cov_strategies();
m_scheduler.run_all();
begin
te = m_scheduler.zetta_cdma_sequence_gen();
te.delete();
end
endtask
........
endclass |
Tool generated code:
The base sequence class (zetta_cdma_sequence) will be overridden with the tool-generated sequence using UVM overriding methods while simulating the code.
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Figure 7 - Constrained randomization and automated functional coverage
Then we can observe that generated coverage reached 99.41% where using normal simulation technique it was 35.41%, as shown in Figure 6.
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Figure 6 - Functional coverage using the automation tool
Using coverage automation, maximum coverage can be reached with the fewest tests. Since all nodes are covered, bugs that are normally hidden will be detected.
CONCLUSION
Automated Functional Coverage, using a tool such as Questa® inFact, is an important aspect of ASIC/SoC verification for checking the functionality of a particular design. The design, Zetta-Hz High Speed CDMA Transceiver, can achieve 100% functional coverage, which indicates that all areas of a design may be tested. Here, we use automation to achieve coverage goals that are 10X to 100X faster and scales up existing coverage of designs.
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