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"Stu Sutherland and Joe Daniels will be greatly missed. I’d like to dedicate this issue to them."
—Tom Fitzpatrick
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As many of you who have been long-time readers of Verification Horizons know, I usually like to spend a little time in these Editor’s Notes relating an anecdote about my family and tying it back to a trend or theme in our industry related to the articles in that issue. But this time around, I feel moved to write about two members of our EDA family who were taken from us too soon this year.
Stu Sutherland passed away this summer, shortly after DAC. I first met Stu over twenty years ago when we were both working on what was then Verilog-1995. Since that time, we continued to collaborate on standards, including IEEE 1364 and IEEE 1800. In addition to being a key technical contributor to these standards, I’m not sure that many people outside of that process know just how much work Stu actually did as technical editor in merging 1364 and SystemVerilog 3.0 from Accellera into IEEE 1800. The word “Herculean” might come close to describing it. His efforts continued as editor through the most recent release of IEEE 1800. Stu was one of the premier independent Verilog educators in our industry as well as a prolific author of books and technical papers. I had the honor of co-authoring a few papers with Stu over the years. To all of these accomplishments, Stu always brought an unfailing sense of decency, humility and serenity that one could not help but treasure. To be able to have called Stu a friend as well as a colleague is truly one of the highlights of my career.
Joe Daniels passed away suddenly last week. Joe and I worked together for the past several years on the Accellera Portable Stimulus Working Group, where he served as technical editor. As Vice Chair of the PSWG, I had many interactions with Joe both in group meetings and one-on-ones as we worked through the details of turning the sometimes chaotic contributions from multiple WG members into a coherent standard.
Joe was extraordinarily good at what he did and was always ready to offer valuable advice on many aspects of the standardization process—from meeting management to document organization—and was always encouraging and direct. Whenever he and I spoke, either in person, on the phone or by video chat, he would never let the conversation end without asking how I was doing or how my family was. Joe’s ability to combine this personal touch with his technical depth and clarity made him unique in my estimation.
Stu and Joe will be greatly missed, and so this issue is dedicated to them.
We have four articles in this issue, but what we lack in quantity we more than make up for in quality. We start with "FPGA Verification Challenges and Opportunities" from my friend and colleague Harry Foster. As you may know, Harry has been the brains behind our biennial Wilson Research Group survey of the EDA industry to discern trends in a variety of design and verification areas. This article will trace some of the key findings for the FPGA segment of the industry over the past several years. I always love it when we get objective data that show that many of the verification techniques we’ve been advocating for years actually serve to reduce the number of bugs that escape into production.
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Next, we continue our Portable Stimulus series by another friend and colleague of mine, Matthew Ballance, with "Building a Better Virtual Sequence with Portable Stimulus.” Virtual sequences in UVM can be some of the most challenging pieces of your verification environment to create such that they are both useful and, importantly, reusable. This article will show how you can use Portable Stimulus to create scenarios for your block-level verification environment that are more robust and flexible than writing a virtual sequence. It’ll also show you how to make the virtual sequence customizable and reusable as you move up to the subsystem level – both of which are very hard to do with a virtual sequence in UVM.
In "A New Approach to Low-Power Verification: Power Aware Apps," you’ll learn how to take advantage of some new information-model package functions in UPF 3.0, together with some Tcl code using the information model API, to create some powerful (pardon the pun) apps to help with various aspects of verifying low-power designs. By following the examples and case studies presented, you should be able to replicate the work on your low-power design project. A version of this article was published at DVCon-Europe 2018, but we wanted to share it with you.
We complete this issue with "Simplifying Mixed-Signal Verification" from my Analog Mixed-Signal colleagues at Mentor. If you’re facing a mixed-signal design for IoT, automotive, communication, industrial or any other application, you’ll find this discussion of AMS methodologies to be very helpful. The article wraps up by showing how Mentor’s new Symphony Mixed-Signal Platform provides the flexibility, accuracy, and performance you’ll need to verify the analog portions of your design alongside your digital design. You’ll also see some advanced debugging capabilities of Symphony that will really make your verification productivity sing.
With the loss of Stu and Joe, our industry has lost two of its finest, not to mention a tremendous amount of institutional knowledge. The rest of us will go on, and as I have learned in the past few months, life is too short not to appreciate the outstanding people we are blessed to work with in this industry, regardless of the companies we work for. Take a moment to hug your family members, and the next time you’re talking to a colleague about work, be sure to ask how things are going outside of work. May God bless you and your families, and Godspeed, Stu and Joe.
Respectfully submitted,
Tom Fitzpatrick
Editor, Verification Horizons
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