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Introduction
The open standard ISA (Instruction Set Architecture) of RISC-V is at the forefront of a new wave of design innovation. The flexibility to configure and optimize a processor for the unique target application requirements has a lot of appeal in emerging and established markets alike. RISC-V can address the full range of compute requirements such as an entry-level microcontroller, a support processor (for such functions as power management, security etc.), right up to the state-of-the-art processor arrays with vector extensions for advanced AI (Artificial Intelligence) applications and HPC (High-Performance Computing).
This wave of innovation is generating a tsunami in verification as more and more SoC development teams face the
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