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  • Home
  • Verification Horizons
  • February 2013
  • System Level Code Coverage using Vista Architect and SystemC

System Level Code Coverage using Vista Architect and SystemC

Verification Horizons - Tom Fitzpatrick, Editor

System Level Code Coverage using Vista Architect and SystemC by Ken P. McCarty, Mentor Graphics

INTRODUCTION

SoC are constantly becoming more and more complex forcing design teams to eke out as much performance as possible just to stay competitive. Design teams need to get it right from the start and can't wait until it's built to find out how it truly performs. This is where System Level Modeling and SystemC/TLM shine. System Level Modeling enables design teams to get it right from the start and by producing the optimal design the first time through. Vista Architect adds to this giving the designer the ability to quickly assemble a design and analyze the SoC performance before it is ever built. Code coverage will raise the level of confidence in a design.

Code coverage has been around for years. Its roots started in the software development community and can be traced back to the 1960's. In later years it was adapted for use in modern HDL design environment. Today it has become a standard piece of all verification flows and methodology.

Now it's time to move code coverage to the next level … the system level. One of the great advantages of SystemC is, at its core, is just C/C++ (with an additional library call for SystemC). What this means is just about any C/ C++ analysis tools will work with SystemC. The GNU C/ C++ compiler's built-in code coverage mechanisms work perfectly with SystemC and Vista Architect.

THE BENEFITS

It is a huge benefit to have comprehensive Testbenches from the start at the system level. This allows the same testbench, created at the system level, to be reused throughout the design flow. This in itself drastically reduces testbench development and verification time, and it confirms that the functionality implemented at the system is consistent throughout the entire design process and flow. Code Coverage has two main benefits, at the system level, it helps to determine if the testbenches:

  • have covered all of the intended functional components in the design,
  • and, in addition, it can expose components in the design that may not be used in the end product.

Typically, code coverage is used as a performance indicator on a verification strategy. At the system level in can be used to do more. It can be used to expose functionality or components of a design that are redundant or not used. These simple "extra" function or components can take up valuable Silicon real estate, become a hidden power drain, impact the performance, and increase the development time. They drive up product costs and directly impact time to market. These "extra" functions creep into a design process when components are designed individually, but when integrated into a system, become redundant or un-utilized.

System Level Code Coverage gives the architects and designers the opportunity to validate that their verification strategy is comprehensive and the design is optimal. It is important to understand that the System Level Code Coverage is a forward looking strategy, from an architectural perspective. It is preformed even before the first line of the RTL is ever written.

WHAT'S INVOLVED

Vista Architect enhances the use of Code Coverage for SystemC and the TLM based SoC designs. It makes it significantly easier to enable code coverage. Vista Architect separates the SystemC communication and timing from the functional components, thus allowing the coverage criteria to be applied only to the core functionality and not on the SystemC simulation infrastructure. Vista Architect instrumentations are easily bypassed by the coverage tools, enabling the Verification experts to spend productive time on design optimizations.

Setting up a Vista Architect SystemC project for code coverage is very simple. It's just a matter of setting a few options in the Vista Architect GUI, Re-compiling, and running the simulation. The final results are processed and displayed using a simple set of utilities from the command line.

The open source GNU tools "lcov" and "gcov" are frequently used to provide the necessary coverage and metrics for SystemC/C++ language based environment. These tools are easily available on the open source domains, and generate relevant outputs that can be assimilated with the UCDB (Unified Coverage Data Base). Following is an overview of the steps required to run code coverage with Vista Architect and SystemC:

  1. Start Vista architect normally.
  2. Add the code coverage options to the project for the compiler and linker.
  3. Recompile the project.
  4. Run the simulation to completion.
  5. Consolidate coverage data and Generate coverage report.
  6. Review the coverage report in a standard HTML page viewer.

The Code Coverage option only needs to be set up once for a project. Once set up, it's just a matter of recompiling, running the simulation, and analyzing results.

CONCLUSION

The process for running and generating coverage data from Vista and SystemC is straight forward and very easy to implement within any project.

For further information on the coverage tools used here please refer to associated GNU pages on "gcov" and "lcov" internet.

For the complete details of the process please look at the Vista application notes on the use of SystemC/TLM based code coverage.

You can find more information on Code Coverage by searching the Verification Academy website. It contains extensive information on the benefits and usage of code coverage.

Back to Top

Table of Contents

Verification Horizons Articles:

  • What Do Meteorologists and Verification Technologists Have in Common?

  • Using Formal Analysis to "Block and Tackle"

  • Bringing Verification and Validation under One Umbrella

  • System Level Code Coverage using Vista Architect and SystemC?

  • The Evolution of UPF: What's Next?

  • Top Five Reasons Why Every DV Engineer Will Love the Latest SystemVerilog 2012 Features

  • SVA in a UVM Class-based Environment

  • The Formal Verification of Design Constraints

  • OVM to UVM Migration, or "There and Back Again: A Consultant's Tale"

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