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In post-synthesis, gate-level netlist (GL-netlist), power aware (PA) simulation, the fundamental focus is to identify PA specific cells already present in the netlist. The associated UPF with the netlist design, determines the supply network and power connectivity to these special PA cells, and aid to keep their outputs from being corrupted. Hence, the GL-netlist-based power aware simulation (PA-SIM) input requirements are mostly the same as for RTL simulation. However, the design-under-verification at this stage is the GL-netlist from synthesis, so logic gates from standard, multi-voltage (MV), and Macro cell Liberty libraries are already inserted or instantiated in the design. Hence PA-SIM at post-synthesis also requires Liberty
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