Effective Identification of Reset Tree Bugs to Mitigate RDC Issues

As design complexity continues to increase, the task of verifying these designs becomes increasingly challenging. The prevalence of asynchronous resets makes it essential to ensure data stability between different reset domains, using reset domain crossing (RDC) static verification tools to prevent metastability and unpredictable behavior – similar to the challenges and solutions seen with clock domain crossings (CDC).

Determining the reset tree structure within an SoC design can be accomplished using static analysis techniques. This process involves analyzing the RTL of the design to identify and classify reset signals. Initially, resets are recognized through synthesis. They are then categorized based on three characteristics: type (synchronous or asynchronous), activation behavior (active high or active low) and usage (set or reset). Classification is crucial because it allows designers to understand the behavior and interactions of different reset domains, ensuring that reset signal crossings are properly managed and minimizing the risk of timing-related errors or metastability.

Once the reset signals are identified, they are grouped based on their origin within the design. Some resets may be directly controlled by primary inputs, while others might be gated/combinational resets, latch resets, mux resets, soft resets or resets generated by a reset synchronizer circuit (refer to figure 1).

By performing this detailed static analysis, engineers can build a comprehensive reset tree structure, essential for ensuring the proper functioning of complex SoC designs. The reset tree provides the necessary information by tagging sequential elements in a design with their respective reset domains, which helps in tracking the flow and behavior of reset signals throughout the design.